Embebbed software engineer

GMV
Tres Cantos, Spain
2 days ago

Role details

Contract type
Temporary contract
Employment type
Full-time (> 32 hours)
Working hours
Shift work
Languages
English

Job location

Remote
Tres Cantos, Spain

Tech stack

Software Debugging
Digital Electronics
Field-Programmable Gate Array (FPGA)
Reduced Instruction Set Computing
Static Timing Analysis
SystemVerilog
Verilog
VHDL
Vivado
Application Specific Integrated Circuits
Backend
Information Technology

Job description

As part of the GMV Receivers team, you will have a key role in projects related to receiver technology, contributing to the development of projects and products with strong involvement in R&D activities.

You will participate in migrating an arquitecture currently implemented on Xilinx MPSoC / FPGA to an ASIC solution. Additionally, you will have the opportunity to work on the analysis of the existing design, identification of reusable blocks, adaptation of the hardware architecture, and definition of the ASIC implementation flow.

Your main tasks would be:

  • Define and evolve the target architecture for ASIC.
  • Develop and adapt RTL blocks (VHDL/Verilog/SystemVerilog).
  • Analyze and optimize internal interfaces (buses, memories, synchronization, clocks, and resets)
  • Participate in functional verification, simulation, and design debugging.
  • Contribute to the ASIC flow: synthesis, timing analysis, CDC/RDC, DFT, and design closure.Document architecture, technical decisions, and validation results.

Requirements

Do you have experience in SoC?, For this role, we are looking for graduates in Electronic Engineering, Telecommunications, Computer Science, or similar, with a specialization in the field of digital hardware programming.

Additionally, we are seeking profiles with knowledge of digital RTL design, FPGA , SoC or MPSoC architectures, internal buses, IP integration, and functional verification; as well as previous experience in ASIC flow and handling simulation and synthesis tools.

We will also value previous knowledge of STA, DFT, scan, low-power, UPF, floorplanning or backend; verification with SystemVerilog, UVM, assertions or cocotb; embedded ARM/RISC-V processors and hardware/software partitioning; and experience with Synopsys, Cadence, Siemens EDA, Vivado, or Vitis tools.

Benefits & conditions

Pulled from the full job description

  • Dental insurance, Hybrid working model and 8 weeks per year of teleworking outside your usual geographical area.

Flexible start and finish times, and intensive working hours Fridays and in summer.

Personalized career plan development, training and language learning support.

National and international mobility. Do you come from another country? We can offer you a relocation package.

Competitive compensation with ongoing reviews, flexible compensation and discount on brands.

Wellbeing program: Health, dental and accident insurance; free fruit and coffee, physical, mental and financialhealth training, and much more!

  • ️ In our recruitment processes you will always have telephone and personal contact, face-to-face or online, with our talent acquisition team. In addition, bank transfers and bank cards will never be requested. If you are contacted through any other process, please write to our team at privacy@gmv.com

️We promote equal opportunities in recruitment, and we are committed to inclusion and diversity.

WHAT ARE YOU WAITING FOR? JOIN US

#LI-Hybrid If you have any questions please do not hesitate to contact Carolina Barber Caso, in charge of this vacancy.

Carolina Barber Caso

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