> Markdown version of [/jobs/ext/100873-senior-digital-verification-engineer](https://www.wearedevelopers.com/jobs/ext/100873-senior-digital-verification-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior Digital Verification Engineer - **Company:** microTECH Global Limited - **Location:** Edinburgh, UK - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Systems Engineering, C++ (Programming Language), Software Debugging, Python (Programming Language), Oracle Virtual Machine, Specman, System on a Chip, SystemVerilog, Tcl (Programming Language), Verilog - **Published:** May 20, 2026 - **Apply:** https://find.jobs/jobs-near-me/senior-digital-verification-engineer-edinburgh/2775796277-2/ ## About the Role * Bachelor's or higher in Electrical/Electronic Engineering (or equivalent) * Strong experience in SystemVerilog, UVM/OVM, Specman, Verilog, C/C++, ASM, TCL/TK, Python * Knowledge of embedded SoC design and verification lifecycle * Familiarity with CPU, memory, and I/O microarchitectures * Experience with mixed-signal testbenches, behavioral models, constrained random verification, and bus-functional model development * Ability to define tasks, track progress, and deliver quality results Skills & Attributes * Strong analytical and debugging skills * Detail-oriented and quality-focused * Collaborative, team-oriented, with strong communication skills ## Description Join a cutting-edge verification team in Edinburgh, working on state-of-the-art automotive power ICs and embedded SoCs in a hybrid, innovative environment., * Develop verification plans from microarchitecture specifications * Create and maintain SystemVerilog/UVM verification environments * Define and execute test plans, UVM-SV test environments, and functional coverage * Analyze results, enhance coverage, and debug unexpected behavior * Run and maintain regression suites * Lead or participate in verification reviews * Collaborate with System Engineering on requirements * Build mixed-signal testbenches, checkers, and bus-functional models * Apply constrained random verification methodologies * Track deliverables and ensure on-time, high-quality execution ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [When testing just doesn’t cut it](https://www.wearedevelopers.com/videos/720-when-testing-just-doesn-t-cut-it) ## Related Articles - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Fully Remote Software Engineer Jobs](https://www.wearedevelopers.com/magazine/447-fully-remote-software-engineer-jobs) - [Where To Find Software Engineering Jobs](https://www.wearedevelopers.com/magazine/396-where-to-find-software-engineering-jobs) - [Where to Find Entry-Level Software Engineering Jobs](https://www.wearedevelopers.com/magazine/397-where-to-find-entry-level-software-engineering-jobs) - [What’s the Difference between a Junior, Mid, and Senior Developer?](https://www.wearedevelopers.com/magazine/238-what-s-the-difference-between-a-junior-mid-and-senior-developer) - [7 Important Tips That Every Software Developer Should Know](https://www.wearedevelopers.com/magazine/101-7-important-tips-that-every-software-developer-should-know)