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# Staff SWE, Compiler Architect, System Performance Modeling

- **Company:** Google LLC
- **Location:** Kirkland, WA, United States
- **Experience:** Experienced
- **Salary:** $207,000.0 - $301,000.0
- **Contract:** Permanent contract
- **Skills:** Data Analysis, C++ (Programming Language), Compilers, Data Visualization, Software Debugging, Python (Programming Language), Machine Learning, Open Source Technology, Software Architecture, Systems Architecture, Large Language Models, Hardware Acceleration, Machine Learning Operations
- **Published:** June 20, 2026
- **Apply:** https://dejobs.org/x/x/6EBA3EDBED5143FAA00DE4013D881110/job/

## About the Role

Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain., * Bachelor's degree or equivalent practical experience.

 * 8 years of experience programming in C++ or Python.
 * 5 years of experience testing, and launching software products.
 * 5 years of experience with performance, large-scale systems data analysis, visualization tools, or debugging.
 * 3 years of experience with software design and architecture., * Experience with hardware/software co-design problems, especially performance analysis and bottleneck identification at the pre-silicon stage.
 * Experience with ML system architectures, including knowledge of compilers, Intermediate Representations (IRs), and hardware accelerators.
 * Experience enabling and optimizing large-scale ML models (e.g., LLMs, large embedding models).
 * Ability to lead technical strategy for complex systems, influencing both simulation toolchains and hardware roadmaps.
 * Proven expertise in constructing custom IR dialects and leveraging open-source compiler frameworks (MLIR, XLA) to solve system level analysis and exploring software-hardware mapping opportunities.
 * Expertise in architecting high-confidence, high-velocity system performance modeling and correlation infrastructure.

## Description

* Establish and maintain high-confidence correlation infrastructure between simulated performance and physical hardware measurements (silicon).
 * Architect and evolve the simulation layer to support deep exploration of complex, business-critical workloads (e.g., large language models, advanced kernels) and future system topologies.
 * Identify and solve system-level hardware/software bottlenecks and optimization opportunities at the critical pre-silicon stage.
 * Provide high-confidence lower-bound performance estimates for future ML systems and architectures.


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