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# RTL Design Engineer

- **Company:** Intel Corporation
- **Location:** Santa Clara, CA, United States
- **Salary:** $105,650.0 - $200,340.0
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Logic Synthesis of Circuits, Microprocessors, Perl (Programming Language), Formal Verification, Python (Programming Language), Oracle Virtual Machine, Perforce, SystemVerilog, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), ModelSim, Git, Physical Design, Software Version Control
- **Published:** May 14, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3264178726&tx=ZT2423TTI&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

Minimum Qualifications * The candidate must have a Bachelor's Degree in Electrical or Computer Engineering or any STEM related education with at least 2+ years of experience -OR- Master's Degree in Electrical or Computer Engineering * At least 1+ years of coursework or experience in the following areas: o Basic Logic Design o Microprocessors o Computer Architecture o Digital design and RTL coding o Verilog/SystemVerilog and/or VHDL o Synthesis tools (Design Compiler, Genus) o Scripting languages (Python, Perl, TCL)

Preferred Qualifications * Experience with advanced verification methodologies (UVM, OVM) * Knowledge of low-power design techniques * Understanding of physical design constraints and timing closure * Experience with version control systems (Git, Perforce) * Experience with simulation tools (ModelSim, VCS, Xcelium)

## Description

Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs. Participates actively in the definition of architecture and microarchitecture features of the CPU being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Documents micro architectural specs (MAS) of the CPU features being designed. Supports SoC customers to ensure highquality integration of the CPU block.


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