> Markdown version of [/jobs/ext/1185962-asic-digital-design-principal-engineer](https://www.wearedevelopers.com/jobs/ext/1185962-asic-digital-design-principal-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # ASIC Digital Design, Principal Engineer - **Company:** Synopsys, Inc. - **Location:** Theale, UK - **Contract:** Permanent contract - **Skills:** Logic Synthesis of Circuits, Ethernet, Formal Verification, Network Protocols, PCI Express, SystemVerilog, Application Specific Integrated Circuits, Software Verification - **Published:** July 5, 2026 - **Apply:** https://uk.indeed.com/viewjob?jk=a6b2fd793a55be68 ## About the Role An experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders. Your ability to mentor and lead junior engineers is a testament to your extensive experience in the field. You thrive in a collaborative environment and are committed to continuous learning and improvement., * Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB). * Proficiency in System Verilog, SVA and UVM methodologies. * Strong understanding of digital design and verification concepts. * Familiarity with wider digital ASIC and IP development flow, including RTL design through synthesis. * Experience with simulation tools such as VCS, Model Sim, or similar. * Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges. * Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders. Who You Are: * Detail-oriented with a strong analytical mindset. * Excellent communicator, able to convey complex technical concepts clearly. * Collaborative team player who thrives in a dynamic environment. * Proactive and self-motivated, with a commitment to continuous learning. * Mentor and leader, capable of guiding and developing junior engineers. The Team You'll Be A Part Of: You will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges. You will have the opportunity to work alongside industry experts and contribute to the development of next-generation technologies. ## Description * Designing, implementing and optimizing verification environments to ensure the correctness of Interface IP protocols. * Creating, executing and tracking against detailed test plans to verify complex ASIC designs. * Developing and maintaining verification IP and testbenches using System Verilog and UVM. * Collaborating with design and architecture teams identifying fix bugs. * Performing functional coverage analysis and driving coverage closure. * Mentoring and guiding junior verification engineers in best practices and methodologies. The Impact You Will Have: * Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications. * Enhancing the robustness and efficiency of our verification processes and methodologies. * Contributing to the successful launch of Interface IP products, impacting various industries. * Driving innovation and excellence within the verification team. * Improving the overall performance and functionality of Synopsys' IP offerings. * Fostering a culture of continuous improvement and technical excellence. ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [The Gashlycrumb Tinies of AI Networking You Must Know (or Languish!)](https://www.wearedevelopers.com/videos/2067-the-gashlycrumb-tinies-of-ai-networking-you-must-know-or-languish) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Docker network without Docker](https://www.wearedevelopers.com/videos/1418-docker-network-without-docker) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) ## Related Articles - [How software is steering vehicle technology](https://www.wearedevelopers.com/magazine/515-how-software-is-steering-vehicle-technology) - [What is Software Engineering?](https://www.wearedevelopers.com/magazine/289-what-is-software-engineering) - [Welcome to Switzerland](https://www.wearedevelopers.com/magazine/4-welcome-to-switzerland) - [Navigating the AI Shift](https://www.wearedevelopers.com/magazine/629-navigating-the-ai-shift) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Events like RSAC Get You CISOs. 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