> Markdown version of [/jobs/ext/1186555-senior-staff-design-for-test-engineer](https://www.wearedevelopers.com/jobs/ext/1186555-senior-staff-design-for-test-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior/Staff Design for Test Engineer - **Company:** OLIX - **Location:** Bristol, UK - **Experience:** Expert - **Salary:** £321,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Code Coverage, Software Debugging, Logic Synthesis of Circuits, Firmware, Joint Test Action (IEEE Standards), Python (Programming Language), Open Source Technology, SystemVerilog, Tcl (Programming Language), Test Execution Engine, Strategies of Testing, Verilog, VHSIC Hardware Description Language (VHDL), Application Specific Integrated Circuits, Hardware Acceleration - **Published:** July 5, 2026 - **Apply:** https://uk.indeed.com/viewjob?jk=5d377de2a23e9fcb ## About the Role * 7+ years of hands-on DFT architecture, implementation, and verification for high-performance ASICs or SoCs, including ownership of at least one product with comprehensive DFT coverage. * Proven success implementing and verifying advanced DFT features (e.g., Scan/ATPG, Boundary Scan, Memory BIST/Repair) on multi-hundred-MHz to multi-GHz clock domains. * Expertise with industry-standard EDA flows: Scan insertion, ATPG, pattern simulation (gate-level), fault modeling, and diagnosis tools. * Demonstrated proficiency with DFT flows: compression techniques, EDT, JTAG/IEEE 1149.1/1687, and managing large pattern sets. * Proficiency using Python/Tcl scripting for DFT flow automation, pattern generation/management, and silicon debug/bring-up. * Solid grounding in semiconductor device physics, fault models (stuck-at, transition, bridging), and yield enhancement strategies. * Excellent communication and cross-functional collaboration abilities; thrives in a fast-moving, ambiguous environment. Nice to have * Tape-out experience at 22 nm or below. * Knowledge of high-speed SerDes or HBM/DDR DFT challenges. * Familiarity with AI/ML workloads or systolic arrays and their implications for DFT. * Contributions to open-source DFT tools or verification frameworks. ## Description We are seeking highly skilled and motivated Senior/Staff DFT (Design for Test) Engineers with a strong focus on high-performance digital design to take end-to-end ownership of robust, testable silicon, from early test strategy definition to verified DFT implementation, pattern generation, and silicon bring-up. You will join a multidisciplinary group creating next-generation accelerators where digital, optical, and mixed-signal domains intersect. The ideal candidate will have extensive experience in the DFT of large-scale, high-volume ASICs and a passion for developing reliable, high-coverage test architectures that drive breakthrough AI hardware, * Architect, own, and implement the comprehensive Design-for-Test (DFT) strategy for complex high-throughput digital pipelines in advanced CMOS nodes, ensuring high test coverage and efficient test execution. * Lead the integration and verification of all DFT features, including Scan, JTAG, Boundary Scan, and Memory BIST, ensuring adherence to industrial standards and sign-off criteria. * Partner with the test engineering team to develop, validate, and optimize ATE-compatible test patterns (stuck-at, transition, bridging, etc.) to achieve aggressive fault coverage and maximise manufacturing yield. * Drive RTL development (SystemVerilog / Verilog / VHDL) with a focus on DFT architecture, including synthesis constraints for test structures, and collaborate on formal and constrained-random verification of DFT logic. * Analyse and minimise the DFT impact on power, performance, and area (PPA), implementing innovative techniques for efficient test access and execution. * Collaborate with mixed-signal and software teams to define and optimise DFT interfaces, test modes, and firmware abstractions for test control and diagnosis. * Mentor junior engineers, lead DFT design reviews, and champion best-practice methodologies for testability and debug across the ASIC development lifecycle. ## Related Videos - [Mutation Testing and Fuzzing in C#](https://www.wearedevelopers.com/videos/703-mutation-testing-and-fuzzing-in-c) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [Are you still programming unit tests or already generating?](https://www.wearedevelopers.com/videos/722-are-you-still-programming-unit-tests-or-already-generating) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Test-reduction - Doing more with less](https://www.wearedevelopers.com/videos/977-test-reduction-doing-more-with-less) ## Related Articles - [The 8 Best Code Testing Tools](https://www.wearedevelopers.com/magazine/402-the-8-best-code-testing-tools) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [Should senior developers refuse interview coding challenges?](https://www.wearedevelopers.com/magazine/29-should-senior-developers-refuse-interview-coding-challenges) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Why developer experience matters](https://www.wearedevelopers.com/magazine/514-why-developer-experience-matters) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers)