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# ASIC Digital Design, Sr Staff Engineer

- **Company:** Synopsys
- **Location:** Boxborough, MA, United States
- **Experience:** Expert
- **Salary:** $138,000.0 - $208,000.0
- **Contract:** Permanent contract
- **Skills:** Software Debugging, Logic Synthesis of Circuits, Perl (Programming Language), Python (Programming Language), Static Timing Analysis, Tcl (Programming Language), Verilog, Scripting, Application Specific Integrated Circuits
- **Published:** July 5, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=d0c9ad93e72b681f

## About the Role

You are an experienced ASIC digital designer or verifier who thrives on solving complex technical challenges. You have strong Verilog and scripting skills, understand front-end flows, and enjoy collaborating with diverse teams. Your curiosity and adaptability help you grow and deliver outstanding support to customers and colleagues., The ideal candidate will specialize in one of the following, experience in multiple areas would be a bonus:

 * ASIC RTL design and verification experience.
 * Verilog, PERL, TCL, Python skills.
 * Static timing analysis and synthesis knowledge.
 * Simulation and debugging abilities.
 * HBM/DDR protocol experience is an asset., * Analytical, collaborative, adaptable.
 * Strong communicator and problem solver.
 * Customer-focused and proactive.

## Description

* Creating and debugging test benches and test cases.
 * Running RTL and gate-level simulations.
 * Supporting application engineers and customers on HBM/DDR PHY topics.
 * Contributing to technical documentation.
 * Driving product improvements based on customer feedback.

The Impact You Will Have:

 * Accelerate deployment of HBM and DDR PHY IP solutions.
 * Enhance product reliability and customer satisfaction.
 * Support innovation through expert guidance.
 * Improve Synopsys' products with your insights.
 * Build lasting customer relationships.


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