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# SOC Engineering, Architect

- **Company:** Synopsys
- **Location:** Sunnyvale, CA, United States
- **Experience:** Expert
- **Salary:** $209,000.0 - $313,000.0
- **Contract:** Permanent contract
- **Skills:** Software Debugging, Software Tools, Signal Integrity, Static Timing Analysis, Subsystems, Scripting, Physical Verification, Physical Design
- **Published:** July 5, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=cfb2fe2c5423dff0

## About the Role

You are an experienced IC physical design expert, with strong leadership in digital implementation and signoff for complex, high-speed mixed-signal subsystems. You thrive in collaborative environments, can manage both local and remote teams, and have a proven track record of driving projects to tapeout. You're hands-on, detail-oriented, and passionate about optimizing performance, power, and area. Your communication skills and technical insight make you a go-to resource for cross-functional teams., * MS in Electrical Engineering; 10+ years in physical design, static timing analysis.

 * Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development & qualification
 * Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.
 * Must have experience in leading and managing local, remote implementation teams.
 * Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.
 * Strong scripting and software skills., * Inclusive leader and effective communicator.
 * Innovative, collaborative, and quality-driven.
 * Thrives in dynamic environments.

## Description

* Technically lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.
 * Guide signoff quality timing constraints development and qualification for critical Subsystem designs with hundreds of clocks.
 * Drive PNR flow and methodology for timing critical muti-million deep sub-micro designs flat/hierarchical digital implementation.
 * Handson expertise in all aspects of flat, hierarchical PNR implementation tasks like synthesis, floorplanning, design partitioning, DFT, low power/UPF based implementation, timing constraints, clock tree synthesis, routing and optimization, extraction, timing signoff, signal integrity, physical verification, Power & IR drop signoff to debug and resolve critical implementation bottlenecks.
 * Requires close interaction and collaborative teamwork with multiple functional groups front end, analog, PM/PEMs.
 * Drive RTL, design partitioning, timing constraints related feedback to Frond-end team for data path optimization, clock & reset architecture improvements for enabling high speed timing closure, PPA improvements.

The Impact You Will Have:

 * Deliver signoff-quality, high-performance silicon solutions.
 * Mentor and develop engineering teams.
 * Drive process improvements and technical innovation.
 * Enhance Synopsys' leadership in high-speed IP.
 * Facilitate successful cross-team collaboration.
 * Enable next-generation chip architectures.


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