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# Design Engineer

- **Company:** Lumilens Inc.
- **Location:** San Jose, CA, United States
- **Experience:** Experienced
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Perl (Programming Language), Field-Programmable Gate Array (FPGA), Design of User Interfaces, Python (Programming Language), PCI Express, Data Streaming, SystemVerilog, Tcl (Programming Language), Network Switches, Scripting, Backend
- **Published:** July 8, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=a644a618f7d10aee

## About the Role

* BS or MS in Electrical/Computer Engineering (or equivalent experience).
 * 3+ years of digital RTL design in SystemVerilog, with blocks taken from micro-architecture through to verification handoff.
 * Solid digital design fundamentals: pipelining, FSMs, FIFOs, clock-domain crossing, and streaming/bus interfaces (e.g., AXI).
 * Lint and CDC/RDC discipline and clean-RTL practices.
 * Power- and timing-aware design practices; comfort with synthesis and timing closure, working with the backend team.
 * Strong debug skills in simulation; scripting in Python, Perl, or TCL.

Preferred

 * High-speed datapath, SerDes-adjacent, or interface design exposure (UCIe, PCIe/CXL, or similar).
 * FEC/coding datapath familiarity (e.g., Reed-Solomon) and gray-code mapping.
 * Assertion-based verification (SVA) and familiarity with UVM block-level testbenches; emulation / FPGA prototyping experience.
 * Exposure to scale-up / scale-out interconnects or network switch / NIC / memory-controller datapaths.
 * Low-power / UPF and DFT (scan) concepts.
 * Optical transceiver, CPO, or linear-drive optics background; advanced-node (N5/N3/N2) design experience.

## Description

* Develop block-level micro-architecture for your assigned blocks, and contribute to interface and register definitions.
 * Design and implement front-end RTL blocks in SystemVerilog - datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.
 * Integrate IP and support parameterization for configurability.
 * Write clean, lint-clean, CDC/RDC-clean RTL that follows the coding and quality standards.
 * Write block-level testbenches, sanity checks, and assertions (SVA) for your own blocks before handoff to DV.
 * Power- and timing-aware design - managing block activity, clock-gating, pipelining, and retiming; partner with the backend team on physical closure for your blocks.
 * Bring-up and debug across simulation and emulation / FPGA prototyping; support DV and silicon bring-up, including DFT/debug hooks in your blocks.
 * Collaborate with the architecture, modelling, DV, DFT, and backend teams as your blocks move through the flow.


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