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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # STA Engineer - **Company:** Qualcomm - **Location:** Santa Clara, CA, United States (Remote available) - **Experience:** Experienced - **Salary:** $153,200.0 - $229,800.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Bluetooth, Software Debugging, Perl (Programming Language), Formal Verification, Python (Programming Language), PCI Express, Static Timing Analysis, Subsystems, System on a Chip, Tcl (Programming Language), Wireless Access Point, Wi-Fi Technology, Scripting, Application Specific Integrated Circuits, Physical Design - **Published:** July 9, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=91f28a4c8c44dea0 ## About the Role * 6-8 years of experience in ASIC/SoC STA, synthesis (including low power), timing constraint development, Low power checks and functional ECO implementation. * Deep knowledge of Static Timing Analysis (STA), and timing constraints. * Experience with Multi Mode Multi Corner (MMMC) timing closure, OCV/AOCV/POCV, and advanced technology nodes. * Experience with timing closure sign off requirements. * Experience in Synthesis, Logical Equivalence Checking (LEC) (RTL-to-Netlist and Netlist-to-Netlist). * Understanding of SOC clocking and reset methodology and implementation. * Scripting skills in TCL and Perl. * Exposure to Low implementation techniques and design checks (multi-voltage designs, UPF). * Hands-on experience with: + Synopsys Prime Time + Synopsys Design Compiler / Cadence Genus Preferred Qualifications * Implementation of Functional ECOs using Conformal ECO Tool. * Familiarity with Low power design, Bus implementation (AXI/AHB) and Clock Domain Crossing (CDC) * Exposure to physical design flows. * Scripting skills using Python. * Exposure to power estimation using PrimePower (PTPX) * Familiarity with Wi-Fi, Bluetooth, or other wireless SoC design. * Familiarity with peripheral interfaces (PCIe, and USB)., * Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience., Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. ## Description Qualcomm's Wi-Fi SoC organization is seeking an experienced and highly skilled Static Timing Analysis (STA) and Synthesis Engineer to contribute to the development of next-generation connectivity chipsets. This role focuses on driving timing-critical implementation for high-performance, low-power Wi-Fi solutions used across mobile, Access point (WIN), XR, automotive, and IoT platforms. You will collaborate closely with Architecture, RTL design, Design verification, DFT, and physical design teams to deliver high-quality silicon on aggressive schedules. The responsibilities include the following * Timing Analysis: + Drive subsystem-level STA and timing closure for both pre-layout and post-layout phases, with support at full-chip level. + Perform timing analysis using PrimeTime (or equivalent tools) and contribute to full-chip signoff activities. + Identify timing bottlenecks, debug violations, and recommend micro-architectural or implementation-level optimizations. + Develop and validate SDC constraints, including Multi-mode and multi-corner (MMMC) setup, to enable accurate and efficient STA analysis. + Define and manage I/O timing budgets across hierarchical designs. + Provide actionable timing feedback at block/HM, sub-system and full-chip levels, including root cause analysis and ECO guidance. + Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage. + Collaborate with RTL, synthesis, and physical design teams to ensure robust timing closure. * Synthesis & Implementation: + Perform synthesis (including low power), formal verification (LEC), and low-power checks for complex SoCs, sub-systems, and cores. + Validate synthesis QoR and ensure clean handoff to physical design. + Develop, validate, and maintain SDC constraints. + Balance Power, Performance, and Area (PPA) constraints during implementation. + Perform functional ECOs including conformal ECOs * Methodology: + Develop AI-driven flows using TCL, Perl, and Python scripts to automate and enhance efficiency across STA, synthesis, timing-constraint development, ECO implementation, and low-power verification flows. ## Related Videos - [Building a Cross-Platform BLE Client with Kotlin Multiplatform and Kable](https://www.wearedevelopers.com/videos/100250-building-a-cross-platform-ble-client-with-kotlin-multiplatform-and-kable) - [JavaScript? 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