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# Senior Staff Engineer Digital Design iv)

- **Company:** Infineon Technologies AG
- **Location:** München, Germany
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Boolean Algebra, Computer Engineering, Software Debugging, Digital Electronics, Logic Synthesis of Circuits, SystemVerilog, Safety Critical Systems, Physical Design
- **Published:** July 10, 2026
- **Apply:** https://de.indeed.com/viewjob?jk=6706637f622fc912

## About the Role

* A degree (Bachelor/Master) in Electrical Engineering, Computer Engineering, or related field
 * 5+ years of experience in digital design, with a focus on automotive, safety-critical systems, and power management systems
 * Proficiency in RTL coding using System Verilog
 * Knowledge of integration of Analog Mixed-Signal IP
 * Knowledge of Physical Design (PD) and experience with timing closure
 * Experience with debugging digital circuits
 * Strong problem-solving skills and ability to work alone or in a team on complex tasks
 * Excellent communication skills across teams
 * Exposure to functional safety (ISO26262) and cybersecurity (ISO21424) standards is a plus
 * Proficiency in English, German is a plus

## Description

#WeAreIn for jobs that impact everyone's life. What if your ideas could change the way the world connects, powers up, or thinks? As a Senior Staff Engineer Digital Design on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Are you in?, * Own microarchitecture design and specification of clock and microcontroller infrastructure Ips

 * Drive the development of scalable, reusable IPs to meet platform and project needs
 * Collaborate with cross-functional teams, including system architects, software engineers and validation teams, to ensure seamless product integration
 * Collaborate with analog design teams on interface protocols and mixed-signal partitioning
 * Conduct RTL design and implementation of digital logic and integration of clock management analog mixed-signal IPs (e.g., oscillators, PLLs, clock monitors)
 * Deploy power-intent to design (UPF), analyze Clock/Reset domain crossing (CDC/RDC) and ensure DFT/ATPG integration
 * Define timing intent and perform circuit timing closure
 * Perform synthesis and power/performance/area optimization, collaborating closely with the physical design team to achieve design closure
 * Work with verification teams to ensure block-level and system-level verification, addressing any issues identified
 * Ensure designs comply with automotive safety standards, implementing safety mechanisms as required
 * Proactively identify and resolve technical issues related to design, timing, or functionality


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