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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # SoC Architect, Coherent Interconnect - **Company:** Samsung - **Location:** San Jose, CA, United States - **Salary:** $180,200.0 - $297,200.0 - **Contract:** Permanent contract - **Skills:** C (Programming Language), ARM Architecture, C++ (Programming Language), Python (Programming Language), Machine Learning, PCI Express, Subsystems, Systems Architecture, Verilog, VHSIC Hardware Description Language (VHDL), Network Switches, Large Language Models, Caching, Information Technology, Low Latency, Optimization Algorithms, Programming Languages - **Published:** July 12, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=e46a2eff64426ae7 ## About the Role * 15+ years of experience with a Bachelor's Degree in Computer Science/Engineering, or 13+ years of experience with a Master's Degree, or 11+ years of experience with a Ph.D * Deep expertise in SoC architecture, interconnect design, or related fields, with a focus on coherent interconnect architectures * Proficient in cache subsystems: design of coherent caches, optimization of caching policies, implementation of coherence protocols (e.g., MESI, MOESI), and balancing latency, bandwidth, and hierarchy trade-offs * Prior experience working on Network-on-chip (NoC) designs and protocols (e.g., AXI, ACE, CHI etc.) * Experience with high-speed interface protocols such as PCIe, USB, and other standardized interfaces * Strong understanding of system-level design principles and optimization techniques * Skilled in programming languages such as C, C++, Python, and Verilog/VHDL * Solid communication and collaboration skills, with curiosity to navigate ambiguity in a fast-paced, global team environment Preferred qualifications: * Knowledge of memory subsystem design, including existing and emerging JEDEC memory (LPDDR/HBM/DDR) standards * Detailed knowledge of on-device ML for LLMs and traditional CPU/GPU/NPU ML acceleration * Experience with the Android Ecosystem and analysis tools * Experience with Arm Architecture and ecosystem, This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information. ## Description As a SoC Architect, you will contribute to the architecture of SoC memory and cache subsystems for Samsung's premium chipsets, with a strong focus on enabling on-device machine learning. In this role, you will help define and implement innovative, high-performance, and low-power interconnect solutions that enable seamless communication between various IP blocks and subsystems within our SoCs. Your knowledge in SoC and coherent interconnect architectures will drive cutting-edge solutions that power next-generation consumer mobile and adjacent markets. * You design and develop coherent interconnect architectures, including cache coherence protocols, network-on-chip (NoC) designs, and high-speed interface protocols (e.g. AXI, ACE, CHI etc.). * You contribute to the development of interconnect IP blocks, including specification, design, verification, and validation of coherent interconnect protocols and NoC fabrics. * You analyze and optimize interconnect performance, power consumption, and area efficiency (PPA) using simulation tools, modeling, and benchmarking to ensure design excellence and achieve competitive advantage in alignment with Samsung's strategic goals and industry trends. * You seek proactive collaboration with global teams-including system architects, IP designers, and software teams-to help define and optimize SoC architectures, ensure interconnect designs meet system PPA requirements, and seamless integration of interconnect IP into SoC designs. * You take initiatives on moderate-to-complex projects and help advance best practices, build trust, demonstrate ownership and open communications. ## Related Videos - [Unleashing the Full Potential of the Arm Architecture – Write Once, Deploy Anywhere](https://www.wearedevelopers.com/videos/940-unleashing-the-full-potential-of-the-arm-architecture-write-once-deploy-anywhere) - [HTTP headers that make your website go faster](https://www.wearedevelopers.com/videos/1676-http-headers-that-make-your-website-go-faster) - [10M Data Records Lost, Underwater Computing, and Psychedelic Fish - Matthias Geniar](https://www.wearedevelopers.com/videos/1908-10m-data-records-lost-underwater-computing-and-psychedelic-fish-matthias-geniar) - [Event based cache invalidation in GraphQL](https://www.wearedevelopers.com/videos/433-event-based-cache-invalidation-in-graphql) - [Develop on Windows, Deploy on Red Hat Enterprise Linux](https://www.wearedevelopers.com/videos/1600-develop-on-windows-deploy-on-red-hat-enterprise-linux) - [For the Cars and the Curious: Android Drift](https://www.wearedevelopers.com/videos/499-for-the-cars-and-the-curious-android-drift) ## Related Articles - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers) - [Everything a Developer Needs to Know About MCP with Neo4j](https://www.wearedevelopers.com/magazine/604-everything-a-developer-needs-to-know-about-mcp-with-neo4j) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Dev Digest 138 - Are you secure about this?](https://www.wearedevelopers.com/magazine/486-dev-digest-138-are-you-secure-about-this) - [How software is steering vehicle technology](https://www.wearedevelopers.com/magazine/515-how-software-is-steering-vehicle-technology)