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# Design for Test (DFT) Engineer

- **Company:** Info Way Group
- **Location:** United States
- **Experience:** Expert
- **Salary:** $104,000.0 - $124,800.0
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Artificial Intelligence, Boolean Algebra, Code Coverage, Computer Engineering, Software Debugging, Electronic Design Automation, Perl (Programming Language), IEEE Standards Association, Joint Test Action (IEEE Standards), Python (Programming Language), SystemVerilog, Tcl (Programming Language), Strategies of Testing, Verilog, Scripting, Application Specific Integrated Circuits, Software Verification, Physical Design
- **Published:** July 12, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=f7878b2bc8d25a4d

## About the Role

* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
 * 5+ years of hands-on experience in Design for Test (DFT).
 * Strong knowledge of:
 * Scan Insertion
 * Scan Compression
 * ATPG
 * MBIST/LBIST
 * JTAG / IEEE 1149.x standards
 * Experience with one or more of the following tools:
 * Siemens Tessent
 * Synopsys TestMAX
 * Cadence Modus
 * Strong understanding of digital logic design, RTL (Verilog/SystemVerilog), and ASIC/SoC development flow.
 * Experience with fault models including stuck-at, transition, and path delay testing.
 * Familiarity with simulation and verification tools.
 * Strong debugging, analytical, and problem-solving skills.
 * Excellent communication and collaboration abilities., * Experience with AI/ML accelerator or high-performance SoC designs.
 * Knowledge of semiconductor manufacturing test flows.
 * Experience with scripting languages such as Python, Perl, or Tcl for DFT automation.
 * Familiarity with low-power DFT methodologies and IEEE standards.

Preferred Skills

 * Scan Architecture Design
 * ATPG Debugging
 * MBIST/LBIST Integration
 * DFT Verification
 * Silicon Bring-up
 * Fault Coverage Analysis
 * JTAG Boundary Scan
 * RTL Debugging
 * Semiconductor Test Methodologies
 * Cross-functional Collaboration

Pay: $50.00 - $60.00 per hour

Application Question(s):

 * 5+ years of hands-on experience in Design for Test (DFT) - yes/no?
 * Experience with one or more of the following tools

## Description

We are seeking an experienced Design for Test (DFT) Engineer to join our semiconductor engineering team in the Bay Area, CA. The ideal candidate will have hands-on experience in DFT implementation, scan insertion, ATPG, MBIST/LBIST, and test architecture for advanced SoC designs. You will collaborate with design, verification, physical design, and manufacturing teams to ensure high-quality, testable silicon for next-generation AI and semiconductor products., * Design, implement, and validate DFT architectures for complex SoCs and ASICs.

 * Perform Scan Insertion, Scan Compression, and Scan Chain verification.
 * Generate and debug ATPG (Automatic Test Pattern Generation) patterns to achieve high fault coverage.
 * Implement and validate MBIST (Memory Built-In Self-Test) and LBIST (Logic Built-In Self-Test) solutions.
 * Develop and verify DFT logic using industry-standard EDA tools.
 * Perform DFT verification through simulation, pattern validation, and silicon bring-up support.
 * Analyze test coverage and optimize DFT implementation for improved manufacturability.
 * Collaborate with RTL, Physical Design, Verification, and Manufacturing teams throughout the product lifecycle.
 * Support silicon debug, failure analysis, and production test activities.
 * Prepare DFT documentation, test plans, and implementation reports.


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