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# Technical Specialist - Silicon Platform Validation, Python

- **Company:** HCL America Inc.
- **Location:** Santa Clara, CA, United States
- **Experience:** Expert
- **Salary:** $172,000.0
- **Contract:** Permanent contract
- **Skills:** Comsol Multiphysics, Software Debugging, Electronic Design Automation, Perl (Programming Language), Python (Programming Language), Routing, PCI Express, Performance Tuning, Cadence Virtuoso, Signal Integrity, Tcl (Programming Language), Linux Virtual Server, Network Switches, Scripting, Hfss, Physical Design, Ansys
- **Published:** July 13, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=68e0309b3ffc865f

## About the Role

5+ years of experience in silicon interposer design, advanced packaging physical
design, or semiconductor back-end-of-line (BEOL) design

Strong proficiency with physical design and layout tools:
Layout & Routing: Cadence Virtuoso, Cadence APD (Advanced Package
Designer), Synopsys IC Compiler II, Siemens Calibre
Verification: Cadence PVS, Mentor Calibre (DRC/LVS/ERC)
Parasitic Extraction: StarRC, QRC, Calibre xRC

Deep understanding of silicon interposer process technology:
RDL metallization (Cu damascene, semi-additive process)
TSV fabrication (via-first, via-middle, via-last)
Micro-bump and C4 bump technology
Wafer thinning and backside processing
Experience with high-density routing at fine pitch (< 1 µm L/S for RDL, < 10 µm TSV
pitch)
Knowledge of design-for-reliability (DFR): electromigration, stress migration, thermal
cycling, and Cu pumping in TSVs
Familiarity with foundry PDKs and process design kits for interposer technologies
Scripting skills (Python, Tcl, SKILL) for design automation and custom DRC rule
developmen

Technical Environment
Domain Tools & Technologies
Physical Design & Layout Cadence Virtuoso, APD, Allegro SiP, Synopsys IC Compiler II
Verification (DRC/LVS) Cadence PVS, Siemens Calibre, IC Validator
Parasitic Extraction StarRC, QRC, Calibre xRC
EM/Electrical Analysis Ansys HFSS, Cadence Clarity, Sigrity
Thermo-Mechanical Ansys Mechanical, Ansys Icepak, COMSOL Multiphysics
Scripting & Automation Python, Tcl, Cadence SKILL, Perl
Foundry Platforms TSMC CoWoS (S/R/L), UMC, GlobalFoundries, Samsung I-Cube
Interconnect Standards UCIe, HBM3/3E PHY, PCIe Gen5/6, high-speed SerDes

## Description

We are looking for a Silicon Interposer Design Engineer to drive the physical design, layout, and
technology development of silicon interposers used in next-generation 2.5D and 3D
heterogeneous integration platforms. You will own the interposer design from architecture
definition through tapeout, working at the intersection of semiconductor process technology,
package integration, and system-level performance optimization.

Key Responsibilities

Lead the physical design and layout of silicon interposers for multi-chiplet integration
(compute, HBM, I/O, networking dies)
Define interposer architecture including die placement, bump map assignment, RDL
routing strategy, TSV farm layout, and power/ground distribution
Develop and optimize RDL (Redistribution Layer) routing for high-density die-to-die
interconnects, ensuring compliance with electrical, thermal, and mechanical constraints
Design TSV (Through-Silicon Via) arrays and transitions - including TSV placement,
keep-out zones, stress-aware floorplanning, and landing pad optimization
Collaborate with SI/PI engineers to meet signal integrity and power delivery targets
across the interposer
Define and validate interposer stackup (metal layers, dielectric thickness, TSV
dimensions) in coordination with foundry process capabilities
Perform DRC/LVS verification and ensure design compliance with foundry design rules
(TSMC CoWoS, UMC, GlobalFoundries, etc.)
Work with EDA tool flows for interposer-specific design (custom routing, via pillar arrays,
micro-bump pitch optimization)
Co-optimize interposer design with package substrate and PCB teams for seamless
chip-package-board integration
Support thermal-mechanical analysis by providing accurate layout data for warpage,
stress, and reliability simulations
Interface with foundry partners for technology selection, design rule clarification, and
tapeout execution
Drive DFM/DFT strategies to improve yield and testability of interposer-based products
Support silicon bring-up, debug, and failure analysis of interposer-related issues


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