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# DFT Engineer/ SoC DFT Lead

- **Company:** Siri Info Solutions Inc
- **Location:** Santa Clara, CA, United States
- **Experience:** Expert
- **Salary:** $120,000.0 - $135,000.0
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Code Coverage, Computer Engineering, Software Debugging, Perl (Programming Language), Formal Verification, Python (Programming Language), SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Physical Design
- **Published:** July 15, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=15e9c3d469acb769

## About the Role

* BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field. 12+ years of experience in DFT with proven leadership of large SoC programs.
 * Strong expertise in scan insertion, scan compression, ATPG, MBIST, LBIST, boundary scan, and gate-level simulation.
 * Hands-on experience with Siemens Tessent tools and methodologies.
 * Experience implementing and debugging SSN and iJTAG architectures. Strong understanding of multi-clock and multi-power domain SoC designs.
 * Experience with DFT signoff, fault analysis, pattern validation, and silicon debug. Knowledge of synthesis, STA, formal verification, and physical design interactions.
 * Proficiency with Verilog/SystemVerilog and scripting languages such as Tcl, Perl, or Python. Excellent communication, project coordination, and team leadership skills.

Preferred Qualifications

 * Experience with advanced-node SoCs (7nm, 5nm, 3nm or below). Experience with chiplet-based or multi-die architectures.
 * Familiarity with IEEE 1149.1, IEEE 1149.6, IEEE 1500, and IEEE 1687 standards. Experience supporting manufacturing test, yield analysis, and failure diagnostics.
 * Prior experience leading geographically distributed DFT teams.

## Description

SoC DFT Lead with experience to define, architect, and execute Design-for-Test solutions for complex multi-partition SoCs from RTL through silicon bring-up. The successful candidate will lead a team of DFT engineers and work closely with RTL, Physical Design, Validation, and Post-Silicon teams to ensure high-quality test implementation and coverage across the entire chip., * Define and document SoC-level DFT architecture and implementation strategy. Lead DFT execution across block, partition, and top-level integration.

 * Architect and implement scan, scan compression, MBIST, LBIST, boundary scan, SSN, and iJTAG solutions. Plan and manage DFT requirements, schedules, netlist releases, and execution milestones.
 * Coordinate with RTL, Physical Design, Timing, and Validation teams throughout the design cycle. Drive DFT insertion, verification, ATPG generation, fault coverage closure, and pattern signoff.
 * Lead DFT structure verification, gate-level simulations, logic equivalence checks, and pattern retargeting activities. Analyze test coverage, diagnose failures, and support silicon bring-up and production ramp.
 * Mentor and guide DFT engineers and provide technical leadership across projects. Participate in design reviews and ensure DFT readiness at all project milestones.


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