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# Design Verification Engineer (Silicon Engineering)

- **Company:** Space Exploration Technologies Corp.
- **Location:** Austin, TX, United States
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Formal Verification, Python (Programming Language), MATLAB, Object-Oriented Software Development, SystemVerilog, Test Case, Scripting, Application Specific Integrated Circuits, Information Technology, Software Coding
- **Published:** July 16, 2026
- **Apply:** https://www.juju.com/job/00000000ggwwdj

## About the Role

+ Bachelor's degree in electrical engineering, computer science or computer engineering

 + 1+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

 + Advanced degree in electrical engineering or computer engineering

 + Experience with verification methodologies such as UVM

 + Strong object-oriented programming knowledge

 + Strong problem-solving and coding skills

 + Experience in constrained random verification

 + Expertise in developing test plans, implementing coverage models, and analyzing results

 + Experience with scripting languages, e.g. Python for automation

 + RTL design, chip bring-up, and post-silicon validation experience

 + Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

 + Ability to work extended hours and weekends as needed to meet critical milestones, + To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here (https://www.pmddtc.state.gov/?id=ddtc\_kb\_article\_page&sys\_id=24d528fddbfc930044f9ff621f961987) .

## Description

+ Responsible for digital ASIC verification at block and system level

 + Write and review test plans, develop test harnesses and test sequences

 + Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks

 + Responsible for test plan execution, running regressions, code and functional coverage closure

 + Automate test case generation by using Python and MATLAB programs

 + Contribute towards pre-silicon verification, chip bring-up and post-silicon validation

 + Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs


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