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# Staff RTL Design Engineer

- **Company:** ARM
- **Location:** Austin, TX, United States
- **Experience:** Experienced
- **Salary:** $198,100.0 - $268,000.0
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Emulators, PCI Express, SystemVerilog, Verilog, Network Switches, Data Analytics
- **Published:** July 16, 2026
- **Apply:** https://www.disabledperson.com/jobs/73679981-staff-rtl-design-engineer

## About the Role

* BS/MS in Electrical and/or Computer Engineering with between 4-8 years of experience.
 * Good understanding of all stages of the design cycle: initial concept, specification, implementation, verification, documentation and support.
 * Experience with System Verilog RTL design, coupled with design synthesis.
 * Experience with lint/CDC/RDC, SVA, and at least one formal tool (e.g., Jasper/VC Formal) for protocol and liveness properties.
 * Comfortable with synthesis/STA (Design Compiler/Genus, PrimeTime/Tempus) and debug across sim, emulation, and silicon.
 * Good interpersonal and teamwork skills. Clear, data-driven communication.

"Good To Have" Skills and Experience :

 * Experience with interconnect and bus architecture. Interconnect concepts: virtual channels, arbitration, QoS, wormhole/credit flow control, deadlock/livelock avoidance, packetization/flits, PCIe etc.
 * Knowledge of AMBA protocols (e.g. AMBA5 CHI, AMBA5 AXI, ACELite, AMBA5 APB etc.) is a plus.
 * Experience with power aware RTL design methodologies and analysis tools. Low-power design (UPF/CPF), power/clock gating, retention, DVFS.

## Description

As an Interconnect RTL Design Engineer, you will be part of the Systems team focused on next-generation interconnects targeting high-end mobile, automotive, networking, and enterprise markets! You will take part in specification, microarchitecture and RTL design of high-performance, energy-efficient interconnects. You will also be considering functional safety aspects of the design that include exploration, analysis and implementation., As an RTL Design Engineer, you would be accountable for one or more functional units of the Interconnect while working closely with performance modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals. Typical accountabilities include:

 * Understanding the high-level specification and requirements of functional units of Interconnect products.
 * Define the Micro-architecture for a unit and develop Verilog RTL logic design for the unit
 * Using power aware design methodologies, analyzing early results from tools like RTL PowerPro.
 * Collaborate with verification team on the test plan development for the blocks and verification closure
 * Analyze synthesis/timing reports, identify and address critical areas to meet the PPA targets


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