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# Technical Specialist - Silicon Platform Validation, Python

- **Company:** HCL America Inc.
- **Location:** Santa Clara, CA, United States
- **Experience:** Expert
- **Salary:** $172,000.0
- **Contract:** Permanent contract
- **Skills:** Computer Programming, Perl (Programming Language), Ethernet, Python (Programming Language), MATLAB, PCI Express, Tcl (Programming Language), Scripting, Hfss, Ansys
- **Published:** July 17, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=ad71430bf1aef053

## About the Role

5+ years of experience in SI/PI analysis for semiconductor packaging or high-speed
PCB design
Strong proficiency with industry-standard EM and circuit simulation tools:
EM Solvers: Ansys HFSS, Ansys SIwave, Cadence Clarity 3D, Keysight ADS
Momentum
Circuit Simulation: Synopsys HSPICE, Cadence Spectre, Keysight ADS
PDN Analysis: Ansys RedHawk, Cadence Voltus, Sigrity PowerDC/PowerSI
Deep understanding of transmission line theory, Maxwell's equations, and S-parameter
analysis
Experience with high-speed interface protocols (PCIe, UCIe, HBM, DDR, Ethernet
SerDes)
Proficiency in package stackup design, impedance control, and via transition
optimization
Hands-on experience with measurement correlation (VNA, TDR/TDT, near-field
scanning)
Programming/scripting skills (Python, MATLAB, Tcl) for automation and post-processing

Other Requirements

Technical Environment
Domain Tools & Technologies
EM Simulation Ansys HFSS, SIwave, Cadence Clarity 3D Solver, Keysight EMPro
Circuit Simulation HSPICE, ADS, Spectre, SystemVue
PDN Analysis RedHawk-SC, Voltus, PowerSI, PowerDC
Layout/Design Cadence APD/SiP, Synopsys IC Compiler, Mentor Xpedition
Scripting Python, MATLAB, Tcl, Perl
Measurement VNA (Keysight PNA-X), TDR (sampling scope), real-time oscilloscope
Standards PCIe 5.0/6.0, UCIe 1.1, HBM3/3E, DDR5, 112G/224G SerDe

## Description

We are seeking an experienced SI/PI Engineer to join our Advanced Silicon Packaging team. In
this role, you will be responsible for signal integrity and power integrity analysis, modeling, and
design optimization of next-generation multi-die packaging architectures including 2.5D/3D
integration, silicon interposers, and high-bandwidth memory (HBM) interfaces.


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