> Markdown version of [/jobs/ext/1315521-hardware-design-engineer-ethernet-switching](https://www.wearedevelopers.com/jobs/ext/1315521-hardware-design-engineer-ethernet-switching). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Hardware Design Engineer, Ethernet Switching - **Company:** Arista Networks - **Location:** Roseville, CA, United States - **Experience:** Expert - **Salary:** $260,000.0 - **Contract:** Permanent contract - **Skills:** Computer-Aided Design, Artificial Intelligence, Computer Engineering, Data Centers, Software Debugging, Ethernet, Field-Programmable Gate Array (FPGA), Hardware Design, Networking Hardware, PCI Express, Schematic Capture, Signal Integrity, Systems Architecture, User-Centered Design, Verilog, Network Switches, Pcb Layout - **Published:** July 17, 2026 - **Apply:** https://www.dice.com/job-detail/3d20b35f-29f7-4b8b-98a4-02e8429f1ad3 ## About the Role * BSEE or MSEE * 10+ years of relevant experience in hardware engineering * Experience designing Networking Hardware, particularly involving 100G and 200G PAM4 Ethernet switching * Embedded x86/ARM system design is highly desirable * Experience designing 20+ layer count boards featuring 50G+ signals, and advanced PCB manufacturing technologies such as sequential lamination, HDI, and ultra-low-loss materials * Experience working with multi-phase DC/DC's for high current, high transient loads * Experience working with High speed interfaces, such as DDR, PCIe * Writing specifications and drawing schematics for high complexity boards * Working closely with CAD designers on complicated layout and routing * Working closely with Software and test engineers to bring-up and debug systems * Familiarity with signal integrity and power integrity concepts and tools, such as: impedance, PDN's, differential routing, insertion loss, S-parameters, TDR's, VNA's * Experience with mass production Design for Manufacturability (DFM) * FPGA design and system simulation using Verilog * Working with Contract Manufacturers * Successfully taking products from concept to production ## Description Working closely with cross-functional teams including software, product management, and manufacturing, our engineers innovate on system architectures, high-speed PCB designs, and signal integrity to deliver state-of-the-art products that drive network performance and reliability. The total estimated annual compensation range for this position, inclusive of base salary, bonus, and equity, is $260,000 to $470,000. This range is a good faith estimate only. Bonus and equity are discretionary, subject to plan terms, and are not guaranteed components of total compensation. Actual total annual compensation may vary based on employee performance, company or equity performance, company policy, board approval, or similar factors. Please see additional base salary information below. What You'll Do Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyper-scale data centers and bleeding edge AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments. Candidates for this position would be responsible for the entire hardware design process: * Authoring Functional Specifications of high power and high density Ethernet switches used in AI networks * Selecting and Qualifying Components * Schematic Capture (both flat and hierarchical) * Working closely with eCAD teams on PCB layout and component footprints * Working with internal teams to run (or run your own) signal integrity simulations on both power and datapath signals * Specifying PCB stackup and fabrication details with various PCB vendors * Working closely with local and overseas Contract Manufacturers (CM), from proto through production * Lab bring up and debug of prototypes * Driving complex system debug between software, hardware, and test teams * Training CM for high yield test and manufacturing * Guiding groups of engineers and mentoring younger engineers ## Related Videos - [The Gashlycrumb Tinies of AI Networking You Must Know (or Languish!)](https://www.wearedevelopers.com/videos/2067-the-gashlycrumb-tinies-of-ai-networking-you-must-know-or-languish) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) - [How to Domain Model – An example from manufacturing](https://www.wearedevelopers.com/videos/742-how-to-domain-model-an-example-from-manufacturing) - [Docker network without Docker](https://www.wearedevelopers.com/videos/1418-docker-network-without-docker) - [Breaking the Hardware Mindset: Overcoming Barriers to System-Level Innovation](https://www.wearedevelopers.com/videos/1635-breaking-the-hardware-mindset-overcoming-barriers-to-system-level-innovation) ## Related Articles - [Why Event-Driven Architecture Isn’t About Speed (and When You Actually Need It)](https://www.wearedevelopers.com/magazine/745-why-event-driven-architecture-isn-t-about-speed-and-when-you-actually-need-it) - [Dev Digest 129 - Now that's what I call private data!](https://www.wearedevelopers.com/magazine/468-dev-digest-129-now-that-s-what-i-call-private-data) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers) - [Never delegate the understanding](https://www.wearedevelopers.com/magazine/749-never-delegate-the-understanding) - [Graph and AI Trends 2026: Why Is AI Running but Not Yet Delivering?](https://www.wearedevelopers.com/magazine/680-graph-and-ai-trends-2026-why-is-ai-running-but-not-yet-delivering)