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# Sr. SoC Power & Performance Architect, AI Hardware

- **Company:** Tesla Motors
- **Location:** Palo Alto, CA, United States
- **Experience:** Expert
- **Salary:** $160,000.0 - $312,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Computer Engineering, Software Architecture, Information Technology, Optimization Algorithms, Hardware Acceleration
- **Published:** July 17, 2026
- **Apply:** https://diversityjobs.com/main/sendform/8/8/28176/1/17621514?backUrl=%2Fcareer%2F17621514%2FSr-Soc-Power-Performance-Architect-Ai-Hardware-California-Palo-Alto

## About the Role

* Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field or equivalent practical experience
 * Experience with power management, low-power architecture, and power optimization techniques (multi-Vth/power/voltage-domain design, clock gating, power gating, DVFS, AVS)
 * Knowledge of energy-efficient chip design fundamentals and related tradeoffs
 * Understanding of processors (GPU a plus), system-software architectures, and their performance/power modeling techniques
 * Familiarity with performance monitors and simulators used in modern processor architectures
 * Experience across the full product-delivery cycle (definition, architecture, design and implementation, testing, and productization)
 * Strong grasp of performance/power estimation and optimization methodology
 * Minimum 5 years of industry experience related to power/performance estimation and optimization (senior-level candidates with 10+ years in power management or low-power design/methodology strongly preferred)

## Description

The Tesla AI Hardware team is looking for a Sr. SoC Power & Performance Architect to work on industry-leading AI accelerators in Palo Alto, CA. The candidate is expected to define power requirements, drive power-performance trade-off analysis, and lead cross-functional efforts to deliver best-in-class energy efficiency across our custom silicon, from early architecture through mass production.
What You'll Do

 * Lead the definition of power requirements for AI accelerator SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints
 * Own and drive cross-functional teams to deliver on competitive power key performance indicators (KPIs) for one or more major SoC IPs such as the compute fabric, memory subsystem, or multimedia subsystem
 * Propose and drive power and performance optimizations throughout the design process, from concept to mass productization
 * Apply low-power design techniques including multi-VT, clock gating, power gating, and Dynamic Voltage-Frequency Scaling (DVFS/AVS)
 * Drive power-performance trade-off analysis to inform engineering reviews and product roadmap decisions
 * Develop and refine power and performance models for processors and system-software architectures
 * Partner with cross-functional teams (architecture, RTL design, implementation, verification, and performance engineering) throughout the design flow
 * Represent the status of SoC power to the executive leadership team


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