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# Hardware Design Integrity Engineer

- **Company:** Arista Networks
- **Location:** Santa Clara, United States
- **Experience:** Expert
- **Salary:** $130,000.0 - $225,000.0
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Software Debugging, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Hardware Design, Networking Hardware, PCI Express, Signal Integrity, Systems Architecture, Verilog, Scripting, Application Specific Integrated Circuits, Pcb Layout
- **Published:** July 17, 2026
- **Apply:** https://www.dice.com/job-detail/897f7598-9983-44bf-b459-00289894257e

## About the Role

* BSEE or MSEE
 * 5+ years of relevant experience in hardware engineering
 * Experience debugging Networking Hardware
 * Experience with proper design of 20+ layer count boards featuring 50G+ signals
 * Experience debugging and validating multi-phase DC/DC's for high current, high transient loads
 * Experience with design and debug of high speed interfaces (DDR, PCIe) as well as low speed signals (I2C, SPI)
 * Familiarity with signal integrity and power integrity concepts and tools, such as: impedance, PDN's, Bode plots, PCIE analyzers, TDR's, VNA's
 * FPGA design using Verilog

## Description

Working closely with cross-functional teams including software, product management, and manufacturing, our engineers innovate on system architectures, high-speed PCB designs, and signal integrity to deliver state-of-the-art products that drive network performance and reliability.

What You'll Do

Our Hardware Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscaler datacenters and bleeding edge AI clusters. With this comes complex, oftentimes cross-platform issues requiring engineers passionate about debugging and delivering root cause analysis and fixes to the design team, executives, and customers.

Candidates for this position would be responsible for debugging production system problems and delivering solutions.

 * Deep dive into various aspects of any existing hardware design - CPU/ASIC, power, SI, clocking, PCIE, optics, fab, components.
 * Work closely with sw & customer teams on high pressure escalations from the field, including reading logs, identifying the bug, determining the best fix with minimal interruption to the field, delivering the final solution, determining if any other systems are susceptible, and implementing measures to prevent the issue from occurring again.
 * Writing scripts to look for specific information in the logs or to capture information in live debug sessions
 * Work closely with the hw design team, but also be able to make firmware, schematic, BOM, fab changes as needed.
 * Lab measurements and debug.
 * Work closely with component, FA, ODM teams to identify component level or third party RCAs and fixes needed.
 * Identify test escapes. Work with the design validation team to examine current test limitations and develop new tests.
 * Write and present root cause analysis for executives and customers.


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