> Markdown version of [/jobs/ext/1320168-design-for-test-dft-engineer](https://www.wearedevelopers.com/jobs/ext/1320168-design-for-test-dft-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Design-for-Test (DFT) Engineer - **Company:** K2 Space - **Location:** Seattle, WA, United States - **Experience:** Expert - **Salary:** $170,000.0 - $250,000.0 - **Contract:** Permanent contract - **Skills:** Code Coverage, Software Debugging, Joint Test Action (IEEE Standards), Strategies of Testing, Scripting, Physical Design - **Published:** July 17, 2026 - **Apply:** https://www.dice.com/job-detail/2d43d961-b7b6-4af4-b4b8-fbde77201c38 ## About the Role With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we'd love for you to apply., * B.S. or M.S. in Electrical Engineering or related field. * 7+ years of experience in DFT for complex SoCs. * Strong hands-on experience with RTL DFT insertion (scan, compression, test points), and ATPG tools and flows. * Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies. * Experience with low-power DFT techniques. * Familiarity with mixed-signal integration challenges and test methodologies. * Strong debugging skills across RTL, gate-level, and silicon. Nice to Have * Experience with MBIST/LBIST implementation and memory repair flows. * Knowledge of IEEE 1149.x (JTAG/boundary scan) standards. * Experience with multi-voltage domain and power-aware DFT. * Exposure to physical design impacts on DFT (scan chain reordering, congestion, timing). * Scripting experience for automation. * Experience in high-speed interfaces (SerDes) or RF/mixed-signal SoCs. * Prior involvement in A0 silicon bring-up and yield ramp. * Experience working in cross-functional, geographically distributed teams. ## Description We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep expertise in memory BIST and TAP controller insertion at RTL, scan insertion and ATPG, and test strategy development across digital and mixed-signal domains. You will play a critical role in ensuring high test coverage, manufacturability, and first-pass silicon success while collaborating closely with design, verification, and physical design teams., * Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan. * Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies. * Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation. * Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions. * Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.). * Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation. * Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior. * Contribute to methodology development, automation, and flow improvements. ## Related Videos - [Building the Right Product and Building It Right: A Glimpse into Extreme Programming, Atomic Design ](https://www.wearedevelopers.com/videos/398-building-the-right-product-and-building-it-right-a-glimpse-into-extreme-programming-atomic-design) - [JavaScript? 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