> Markdown version of [/jobs/ext/1340355-principal-fpga-asic-engineer-level-3](https://www.wearedevelopers.com/jobs/ext/1340355-principal-fpga-asic-engineer-level-3). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Principal FPGA/ASIC Engineer - Level 3 - **Company:** Northrop Grumman - **Location:** Gilbert, AZ, United States - **Salary:** $79,300.0 - $118,900.0 - **Contract:** Permanent contract - **Skills:** Computer Engineering, Software Debugging, Electronic Design Automation, Field-Programmable Gate Array (FPGA), Hardware Description Language, Static Timing Analysis, Systems Architecture, SystemVerilog, Vivado, Data Processing, Application Specific Integrated Circuits, ModelSim, Power Analysis (Cryptography), Mentor Graphics - **Published:** July 18, 2026 - **Apply:** https://www.juju.com/job/00000000ghc88k ## About the Role The **Principal FPGA/ASIC Engineer will** be responsible for research, requirements analysis and systems architecture, design, coding, test bench design, verification, synthesis and place & route for our Command and Data Handling (C&DH) products. The ideal candidate will have demonstrated expertise in FPGA/ASIC for space applications., + Bachelor's degree in a STEM (Science, Technology, Engineering, and Mathematics) discipline with 5+ years of FPGA design (or related) engineering experience OR Master's degree in a STEM discipline with 3+ years of FPGA design (or related) engineering experience OR Ph.D. in a STEM discipline with 1+ year(s) of FPGA design (or related) engineering experience + Prior work experience in HDL design for an aerospace environment or space application + Proficiency in FPGA design flow including items such as RTL/gate level simulation, synthesis, place & route, static timing analysis, and power analysis + Industry experience in FPGA Design, Simulation and V&V + Must be able and willing to obtain and maintain an active DoD Top Secret clearance Preferred Qualifications: + Advance degree in Electrical or Computer Engineering + Active DoD Top Secret clearance + Experience with Electronic Design Automation (EDA) Tools (e.g., Xilinx ISE/Vivado, Mentor Graphics ModelSim/QuestaSim, Synplify) + Implementation of Digital Signal or Image Processing algorithms on FPGAs + Expertise achieving timing closure on FPGA designs and generating test benches for full functional simulation + Experience working with or developing test benches using System Verilog and Universal Verification Methodology (UVM) + Experience debugging down to the hardware level with experience using Signal Generators, Logic Analyzers, Digital Oscilloscopes and Embedded FPGA Debugging tools ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) ## Related Articles - [Top 6 Hackathons for Developers in 2023](https://www.wearedevelopers.com/magazine/263-top-6-hackathons-for-developers-in-2023) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Dev Digest 134 - Where pixels sing?](https://www.wearedevelopers.com/magazine/477-dev-digest-134-where-pixels-sing) - [Where to Find Entry-Level Software Engineering Jobs](https://www.wearedevelopers.com/magazine/397-where-to-find-entry-level-software-engineering-jobs) - [Why Attend a Developer Event in 2026?](https://www.wearedevelopers.com/magazine/688-why-attend-a-developer-event-in-2026) - [9 Ways to Make Money Hacking](https://www.wearedevelopers.com/magazine/333-9-ways-to-make-money-hacking)