> Markdown version of [/jobs/ext/1368080-director-semiconductor-technologies](https://www.wearedevelopers.com/jobs/ext/1368080-director-semiconductor-technologies). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Director Semiconductor Technologies - **Company:** J. R. C. Company - **Location:** Sunnyvale, CA, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** C++ (Programming Language), Python (Programming Language), Proprietary Software, Cadence Virtuoso, Simulation Software, Static Timing Analysis, Tcl (Programming Language), Linux Virtual Server, Modeling and Simulation - **Published:** July 21, 2026 - **Apply:** https://www.clearancejobs.com/jobs/8890745/director-semiconductor-technologies ## About the Role * Ph.D. in Electrical Engineering, Applied Physics, or a related field with 2+ years of direct industry experience, OR a Master's degree with 6+ years of direct industry experience, OR a Bachelor's degree with 8+ years of experience. * Must be eligible to obtain a U.S. security clearance due to the nature of defense-related projects. * Deep foundational knowledge of semiconductor device physics and semiconductor design methodologies and principles. * Hands-on experience with standard cell design, circuit design, and layout, and associated design tools (e.g. Virtuoso, Spectre, HSPICE) * Demonstrated experience being involved in test-chip designs and MPW execution. * Proficiency in design flows including DRC/LVS, timing analysis, and power integrity. * Extensive experience with semiconductor device & design simulation tools, specifically for library characterization. * Demonstrated track record of managing or leading engineers for a minimum of 5 years. * Demonstrated end-to-end track record of steering execution of complex technical projects from initial concept/feasibility phase through completion. * Outstanding communication and presentation skills Bonus Points * Ph.D. with 5+ years, Master's with 9+ years, or Bachelor's with 10+ years of direct industry experience. * Proven leadership running and scaling high-performing multidisciplinary engineering teams while owning technical strategy and roadmaps. * Demonstrated success shaping government-focused proposals/contracts and contributing to BD pipelines and strategic captures. * Direct RHBD experience mitigating SEU/SEE, plus proficiency in C++, Python, and TCL for advanced simulation and automation. * Hands-on work with advanced FinFET and GAA nodes (e.g., Intel 18A) and a strong ability to rapidly learn new physics and technology platforms. ## Description We are seeking a technically commanding Senior Manager of Semiconductor Technologies to manage our core development efforts in radiation-hardened microelectronics. Reporting directly to the Vice President of Semiconductor Technologies, this role oversees the strategic direction and technical execution of our next-generation LEAP Standard Cell Library and leads the development of proprietary simulation software for predicting reliability and radiation-induced error rates., * Mentor, manage, and grow a high-performing multidisciplinary team of device physicists, circuit designers, and software engineers. * Serve as the subject matter expert on Semiconductor Device Physics for radiation effects, including TID, SEE, and SEU. * Define the technical strategy and roadmap for Radiation Hardened LEAP Standard Cell Libraries across multiple advanced foundry technology nodes. * Interface regularly with government and DoW customers, DIB customers and strategic partners, and attend relevant conferences. Contribute to BD pipeline assessments and capture tracking. Provide hands-on assistance with technical content of capture proposals and work seamlessly with the contracts and proposal execution teams. * Direct the development and enhancement of proprietary software tools used for analyzing circuit reliability and radiation-induced error rates. * Oversee advanced library characterization and simulations to optimize Power, Performance, and Area (PPA) in harsh environments. * Manage relationships with external foundry partners to influence Multi-Product Wafer (MPW) execution and interface directly with customers to ensure technical quality control. ## Related Videos - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Kettle and Pot or Peas in a Pod? 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