> Markdown version of [/jobs/ext/1379849-tpu-soc-design-engineer-google-cloud](https://www.wearedevelopers.com/jobs/ext/1379849-tpu-soc-design-engineer-google-cloud). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # TPU SoC Design Engineer, Google Cloud - **Company:** Google LLC - **Location:** Sunnyvale, CA, United States - **Experience:** Experienced - **Salary:** $116,000.0 - $166,000.0 - **Contract:** Permanent contract - **Skills:** Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Electronic Design Automation, Perl (Programming Language), Python (Programming Language), System on a Chip, SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Google Cloud, Application Specific Integrated Circuits, State Machines, Information Technology, Power Analysis (Cryptography), Code Inspection, Physical Design - **Published:** July 22, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=6cefb83788227271 ## About the Role * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience. * 2 years of experience in ASIC RTL design using systemverilog or verilog. * Experience with industry-standard EDA tools for simulation, synthesis, and power analysis. * Experiecnce with digital design, including synchronous and asynchronous logic, state machines, and bus protocols., * Master's degree or PhD in Electrical Engineering or Computer Engineering, with an emphasis on computer architecture. * 5 years of experience with RTL coding using Verilog/SystemVerilog. * Experience in scripting (e.g., Python, Tcl, or Perl) and debugging with tools like Verdi or VCS. * Experience with SOC implementation standards and interfaces (e.g., AXI). * Experience architecting RTL solutions employing software based construction, instantiation, customization and generation of RTL. * Experience with CDC, UPF, RDC, RTL Linting, and LEC. ## Description * Define and document the microarchitecture for digital designs within the TPU. * Write performant, and power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog. * Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness. * Work with the Physical Design team to meet timing, area, power, and manufacturability requirements. * Contribute to the development and enhancement of design tools, flows, and methodologies. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form. ## Related Videos - [The Cloud is Calling: Answer with In-Demand Skills](https://www.wearedevelopers.com/videos/945-the-cloud-is-calling-answer-with-in-demand-skills) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [JavaScript? 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