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# RTL Design Engineer

- **Company:** Broadcom
- **Location:** Irvine, CA, United States
- **Experience:** Expert
- **Salary:** $127,100.0 - $203,400.0
- **Contract:** Permanent contract
- **Skills:** Software Debugging, Digital Architecture, Perl (Programming Language), Formal Verification, Broadcom, Static Timing Analysis, SystemVerilog, Systems Integration, Verilog, Scripting
- **Published:** July 23, 2026
- **Apply:** https://dejobs.org/x/x/BD67341EBBE646B2A6432F8B189AD382/job/

## About the Role

* MS +10 years of relevant industry experience.
 * Experience with digital implementation flow from RTL synthesis to timing closure.
 * Deep understanding of timing analysis with Primetime flow and generation of Liberty models.
 * Experience with Tessent tool for DFT insertion and verification
 * Proficient with Perl, Python and Tcl scripting.
 * Strong problem solving skills with attention to detail.
 * Must be self-motivated and able to work effectively across internal and external engineering teams.

Highly Desired Qualifications

 * Solid understanding of transistor-level circuit behavior.
 * Familiar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation.
 * Experience with advanced FinFET process nodes , including features, technology limitations and PPA tradeoffs.

## Description

Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and verification of a broad range of analog mixed signal IP and IOs, including leading-edge AI programs on advanced nodes. Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development.

 * Define the digital architecture and verification strategies for complex AMS and IO subsytems
 * Design, synthesis, and verification of Verilog/SystemVerilog RTL.
 * Analysis, debug, and resolution of Lint and CDC issues in the design.
 * Design convergence to timing closure utilizing RTL optimization strategies.
 * Conduct formal verification of design with Synopsys Formality / Cadence Conformal.
 * Generate timing constraints for Synthesis and STA at the block-level and SoC top-level.
 * Drive comprehensive test plans to ensure quality of design.
 * Collaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration.
 * Create and maintain detailed specification, design, and verification documentation.


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