> Markdown version of [/jobs/ext/1399286-ip-integration-engineer](https://www.wearedevelopers.com/jobs/ext/1399286-ip-integration-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # IP Integration Engineer - **Company:** Broadcom - **Location:** Fort Collins, CO, United States - **Experience:** Expert - **Salary:** $129,400.0 - $207,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Bash Shell, Computer Engineering, Cursor (Graphical User Interface Elements), Logic Synthesis of Circuits, Perl (Programming Language), Python (Programming Language), Broadcom, Cadence Virtuoso, Ruby, Static Timing Analysis, SystemVerilog, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Scripting, Application Specific Integrated Circuits, Ansys, GPT - **Published:** July 23, 2026 - **Apply:** https://dejobs.org/x/x/F5B6EA3D942142B78B14F2A2FA3FAAEF/job/ ## About the Role The IP Integration Engineer will be part of a cross functional design team developing die-to-die and die-to-memory PHY IP. The PHYs are used broadly in APD's custom silicon ASIC products. The successful candidate will be involved in the development of the physical composition (hardening of the PHY) as well as developing methodologies for integrating these into large complex 2.5D and 3.5D ASICs. This individual must be highly motivated and capable of working both independently and as part of a team. This position is located in Fort Collins, CO., * A Bachelor's Degree in Electrical or Computer Engineering and 12+ years of related experience; or Masters degree and 10+ years of related experience * Understanding of design trade offs for power, area, and speed in ASIC designs. * Have an understanding of the ASIC design flow including FET design, RTL, synthesis, timing, floorplanning, power planning, P&R, LVS, DRC, ... * Basic understanding of modern FET architecture including FinFET and Gate All-Around (GAA) topologies. * Experience with Cadence Innovus or equivalent toolset * Experience in reading timing reports from static timing tools such as Tempus or Primetime. * Strong verbal, written communication * Team player that can easily work with different personalities and skill levels * Ability to multitask and manage multiple technical issues in parallel * Well organized, methodical, and detail oriented * Must develop, accurately track, and meet commitments to product or engineering development schedules Desired: * Experience with the Cadence Virtuoso design environment * Experience or coursework with RTL languages (i.e SystemVerilog, Verilog, VHDL) * Experience scripting in Skill, TCL, Ruby, Bash, Perl, Python, etc.. * Familiar with timing reports and strategies for fixing violations * Experience or familiarity with Ansys Redhawk * Working knowledge with AI tools such as Chat GPT, Gemini, and/or Cursor ## Description * Work with multiple cross functional teams--analog design, digital design, physical composition, DFT, timing, and customers--to build PHYs * Work with physical composition teams and interposer design teams * Work with analog and physical composition teams to optimize the size and power delivery to high IO density PHYs * Work with teams to analyze power integrity (droop, EM, etc…) in various use cases and workloads * Develop/write PHY integration documentation for ASIC composition teams * Develop list of Checklist task for integration of PHY IP into ASICS * Work with IP build teams to complete quality crosschecks to ensure the quality of the PHYs * Help support customer and ASIC PHY integration questions ## Related Videos - [Cloud Vendor Lock-In - Is it just a new version of the Database Abstraction Layers?](https://www.wearedevelopers.com/videos/1185-cloud-vendor-lock-in-is-it-just-a-new-version-of-the-database-abstraction-layers) - [Coffee with Developers: David Heinemeier Hansson](https://www.wearedevelopers.com/videos/875-coffee-with-developers-david-heinemeier-hansson) - [ Evaluating AI models for code comprehension](https://www.wearedevelopers.com/videos/1462-evaluating-ai-models-for-code-comprehension) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Colorful quantum randomness](https://www.wearedevelopers.com/videos/100257-colorful-quantum-randomness) - [Coroutine explained yet again 60 years later](https://www.wearedevelopers.com/videos/690-coroutine-explained-yet-again-60-years-later) ## Related Articles - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [How software is steering vehicle technology](https://www.wearedevelopers.com/magazine/515-how-software-is-steering-vehicle-technology) - [Dev Digest 166: Sycophancy, Zip bombs and AI Native Development](https://www.wearedevelopers.com/magazine/585-dev-digest-166-sycophancy-zip-bombs-and-ai-native-development) - [Dev Digest 162: AI careers, MCP, AWS best practices & floppy sweaters](https://www.wearedevelopers.com/magazine/571-dev-digest-162-ai-careers-mcp-aws-best-practices-floppy-sweaters) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers)