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# Sr MLA Design Verification Engineer, Cloud-Scale Machine Learning Acceleration - Annapurna Labs

- **Company:** Amazon.com, Inc.
- **Location:** Cupertino, CA, United States
- **Experience:** Expert
- **Salary:** $183,000.0 - $247,600.0
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Computer Engineering, Emulators, Field-Programmable Gate Array (FPGA), Python (Programming Language), Machine Learning, Object-Oriented Software Development, PCI Express, System Testing, SystemVerilog, Network Switches, Scripting, Information Technology
- **Published:** July 23, 2026
- **Apply:** https://dejobs.org/x/x/EAD3FF2F7A2344ECBC370B6EDAB61D1C/job/

## About the Role

* Bachelor's degree or above in Computer Science, Computer Engineering, Electrical Engineering, or related fields
 * 8+ years of design verification experience using System Verilog and UVM
 * 8+ YOE in testbench development including: stimulus, checkers, assertions and coverage, * Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments, and system testing
 * Experience verifying multiple levels of design including: custom blocks, IP blocks, sub-systems, and fullchip SOC system testing.
 * Experience with C/C++ and Object-Oriented Programming.
 * Experience with scripting languages, for e.g. Python.
 * Experience with AMBA protocols, for e.g. AHB/APB/AXI
 * Experience with interconnect protocols, for e.g. PCIe and UCIe
 * Experience with memory sub-systems, including cache coherency and synchronization techniques
 * Experience with verifying complex CPU, GPU, or ML accelerator designs

## Description

* Verify custom chip designs at the SOC level
 * Integrate 3rd party IPs and VIPs into the SOC testbench
 * Create comprehensive testplans, write robust random testcases, and execute coverage plans
 * Maintain autosmoke and regression infrastructure
 * Dive deep into bugs and triages
 * Mentor junior engineers


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