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# RTL Design Engineer

- **Company:** Teradyne Inc.
- **Location:** North Reading, MA, United States
- **Experience:** Expert
- **Salary:** $123,100.0 - $196,900.0
- **Contract:** Permanent contract
- **Skills:** Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Python (Programming Language), Static Timing Analysis, Tcl (Programming Language), Verilog, Scripting, Application Specific Integrated Circuits, State Machines, Physical Design
- **Published:** July 24, 2026
- **Apply:** https://www.juju.com/job/00000000gj3drs

## About the Role

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position.

 + BSEE or MSEE in Electrical Engineering or related field with 5+ years of experience.

 + Extensive logic design experience writing RTL in Verilog

 + Design of state machines, FIFOs, high speed data paths and arbitration logic and DFT

 + Experience with logic synthesis and timing constraints

 + Experience with clock domain crossings (CDC) and static timing analysis (STA)

 + Experience with high speed memory and serial

 + Experience with automation through scripting such as Python, Tcl & Make

## Description

Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is responsible for developing advanced node ASICs for Teradyne next generation products such as SOC and Memory Test Instruments. Teradyne's products in many ways must be ahead of the semiconductor industry in order for our customers to ship production chips/products. You will join a best-in-class Digital team as a RTL Designer working in collaboration with an Analog team and product architects to develop Teradyne's next generation large Mixed Signal ASICs. You will be involved in all phases of development including specification, architecture, design, verification, physical design, and silicon bringup, and will have cutting-edge AI tools available to optimize your productivity., + Developing specifications, micro-architecture, and RTL design of mission critical blocks in collaboration with the chip architect

 + Integration of industry standard and Teradyne custom IPs

 + Collaborating with the verification team on test plans, debug support and coverage closure to ensure high quality RTL and first pass silicon success

 + Providing timing constraints and STA support to the Physical Design team through timing closure


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