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# ASIC Power Engineer, Principal

- **Company:** Positron Ai, Inc.
- **Location:** United States (Remote available)
- **Salary:** $200,000.0 - $300,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Systems Engineering, Firmware, PCI Express, Application Specific Integrated Circuits, Backend, Power Analysis (Cryptography)
- **Published:** July 24, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=ad5491ff55f9c79a

## About the Role

* 12+ years of ASIC design experience.
 * Deep expertise in low-power design techniques and methodologies.
 * Hands-on experience with UPF/CPF power specification and verification flows.
 * Expert-level proficiency with PrimePower and Joules or equivalent power analysis tools.
 * Strong background working with advanced process nodes.
 * A solid grasp of RTL design and its impact on chip power.
 * Proven experience achieving aggressive power targets in production silicon., * Experience with AI accelerator architectures.
 * Familiarity with LPDDR and HBM memory interfaces.
 * Working knowledge of PCIe.
 * Experience with dynamic voltage and frequency scaling (DVFS).
 * Exposure to thermal modeling.
 * Hands-on experience with silicon power validation.

## Description

This role owns power architecture, estimation, optimization, and verification across Positron's AI accelerator roadmap. You will define power methodology from architectural modeling through silicon validation, ensuring industry-leading performance-per-watt while meeting aggressive power and thermal constraints., Power Architecture & Strategy

 * Own the overall chip power strategy, defining approaches for dynamic power, leakage, clock power, memory power, interconnect power, SerDes power, idle power, and peak power.

Power Modeling

 * Develop accurate power models across the full development lifecycle, from early architectural estimation through RTL and gate-level estimation.
 * Perform vector-based and activity-driven power analysis to validate estimates against real workload behavior.

Power Optimization

 * Drive power optimization techniques including clock gating, operand isolation, power gating, voltage islands, and multi-Vt optimization.
 * Apply memory, pipeline, toggle-reduction, and data-movement optimization techniques, including approaches tailored to AI workloads.

Power Integrity

 * Partner with the backend team on IR drop, electromigration (EM), power distribution, and power grid planning.
 * Define power-on sequencing, power domains, reset sequencing, isolation, retention, and UPF/CPF specifications.

Power Verification

 * Own power-aware simulation and UPF verification.
 * Lead reset verification, low-power state validation, wakeup validation, and power sequencing verification.

Cross-Functional Collaboration

 * Partner closely with Architecture, RTL, Backend, Firmware, Thermal, Packaging, and System Engineering teams to align power decisions across the full chip development flow.

AI-Enabled Engineering

 * Use AI-driven tools to improve power analysis, regression triage, power anomaly detection, activity clustering, and identification of optimization opportunities.


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