> Markdown version of [/jobs/ext/1423353-mid-end-asic-engineer-principal](https://www.wearedevelopers.com/jobs/ext/1423353-mid-end-asic-engineer-principal). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Mid-End ASIC Engineer, Principal - **Company:** Positron Ai, Inc. - **Location:** United States (Remote available) - **Experience:** Experienced - **Salary:** $190,000.0 - $280,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Software Debugging, Microprocessors, Electronic Design Automation, PCI Express, Static Timing Analysis, Tcl (Programming Language), Scripting, Graphics Processing Unit (GPU), Application Specific Integrated Circuits, Backend, Physical Design - **Published:** July 24, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=69b784c1092cd153 ## About the Role * 12+ years of ASIC implementation experience, including multiple successful tapeouts. * Expert-level proficiency in synthesis methodology and flow development. * Deep expertise in timing closure across complex, multi-million-gate designs. * Expert-level command of Cadence Genus and/or Synopsys Design Compiler. * Strong SDC expertise, including constraint development and MMMC environments. * A solid grasp of RTL design principles and implementation-friendly coding practices. * Hands-on experience with advanced process nodes at 5nm and below. * Strong Tcl and Python scripting ability for automation and flow development. * Excellent debugging and root-cause analysis skills., * Experience with AI accelerators, CPUs, or GPUs. * Familiarity with LPDDR, PCIe, or SerDes interfaces. * Exposure to chiplet-based architectures and multi-clock SoC designs. ## Description We're looking for an exceptional Principal Mid-End ASIC Engineer to own synthesis, timing convergence, implementation readiness, and logical design quality across our AI accelerator roadmap. This is a deeply technical, hands-on engineering role responsible for transforming high-quality RTL into implementation-ready netlists while driving timing closure strategy, constraint development, physical-aware optimization, and close collaboration between RTL designers and backend implementation partners. You will serve as the technical bridge between architecture, RTL, verification, and physical implementation., Synthesis Methodology & Ownership * Define and own synthesis methodology across current and future ASIC generations, including scalable flows for RTL synthesis, constraint development, timing budgeting, QoR optimization, incremental synthesis, and hierarchical implementation. * Establish signoff criteria and methodology for synthesis deliverables. Hands-On Synthesis & Constraint Development * Own hands-on synthesis using industry-leading EDA tools, including Cadence Genus and Synopsys Design Compiler (or equivalent). * Develop and maintain SDC constraints, clock definitions, false paths, multicycle paths, generated clocks, and MMMC environments. * Drive continuous improvement of synthesis QoR. Timing Closure Leadership * Own logical timing closure and drive optimization across frequency, area, power, congestion, and wireability. * Perform root-cause analysis of timing bottlenecks and develop timing budgets across all chip partitions. * Collaborate closely with architecture and RTL teams to eliminate timing risks before physical implementation. Physical-Aware Optimization * Partner closely with backend implementation engineers to drive physical-aware synthesis, retiming, register balancing, pipeline optimization, logic restructuring, and hierarchical timing budgeting. * Ensure RTL is implementation-friendly from the outset. Cross-Functional Execution * Partner closely with architecture, RTL, verification, physical design, DFT, IP providers, and backend design services to drive rapid issue resolution. Vendor Technical Leadership * Serve as Positron's synthesis technical lead with external implementation partners, reviewing QoR, timing, area reports, and constraint methodology, and defining acceptance criteria. AI-Enabled Engineering * Apply AI to improve timing analysis, QoR regression, constraint generation, timing debug, report analysis, documentation, and engineering automation. ## Related Videos - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [JavaScript? No. Java Scripts! - Scripting with Java](https://www.wearedevelopers.com/videos/2094-javascript-no-java-scripts-scripting-with-java) - [Developing the Backend with Stefan Lingler, CTO at Shpock](https://www.wearedevelopers.com/videos/100360-developing-the-backend-with-stefan-lingler-cto-at-shpock) - [Photonic Computing: Programming a New Class of AI Accelerators (incl. Live Coding)](https://www.wearedevelopers.com/videos/100196-photonic-computing-programming-a-new-class-of-ai-accelerators-incl-live-coding) - [Intermediate Bitcoin Script](https://www.wearedevelopers.com/videos/25-intermediate-bitcoin-script) - [Nest.js - TypeScript in the backend can also be clean](https://www.wearedevelopers.com/videos/1033-nest-js-typescript-in-the-backend-can-also-be-clean) ## Related Articles - [Stephan Gillich - Bringing AI Everywhere](https://www.wearedevelopers.com/magazine/489-stephan-gillich-bringing-ai-everywhere) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Never delegate the understanding](https://www.wearedevelopers.com/magazine/749-never-delegate-the-understanding) - [Navigating the AI Shift](https://www.wearedevelopers.com/magazine/629-navigating-the-ai-shift) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Dev Digest 129 - Now that's what I call private data!](https://www.wearedevelopers.com/magazine/468-dev-digest-129-now-that-s-what-i-call-private-data)