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# Senior Digital ASIC Design Engineer

- **Company:** Brookhaven National Laboratory
- **Location:** New York, NY, United States
- **Experience:** Expert
- **Salary:** $115,000.0 - $145,000.0
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Computer Engineering, Data Transmissions, Software Debugging, Digital Architecture, Digital Technology, Electronic Design Automation, Perl (Programming Language), Network Interface Controllers, Firmware, Field-Programmable Gate Array (FPGA), Joint Test Action (IEEE Standards), Python (Programming Language), Shell Script, Signal Integrity, Static Timing Analysis, System on a Chip, SystemVerilog, Systems Integration, Tcl (Programming Language), Verilog, Serial Peripheral Interface, Application Specific Integrated Circuits, State Machines, Power Analysis (Cryptography), Code Inspection, Physical Design
- **Published:** July 24, 2026
- **Apply:** https://diversityjobs.com/main/sendform/8/8/28176/1/17696552?backUrl=%2Fcareer%2F17696552%2FSenior-Digital-Asic-Design-Engineer-New-York-Upton

## About the Role

* Bachelor's degree in electrical engineering, computer engineering, applied physics, or a closely related field of study
 * Minimum seven (7) years of progressively responsible related work experience in digital ASIC design
 * Demonstrated experience developing synthesizable RTL in SystemVerilog and/or Verilog for complex ASICs or system-on-chip designs
 * Familiarity with ASIC design processes and flows, CAD/EDA tools for ASIC design, and their interoperability across design, verification, synthesis, timing, and physical implementation
 * Experience with digital architecture, clocking and reset strategies, timing constraints, CDC/RDC methodology, low-power design considerations, and debugging of large digital systems
 * Ability to work effectively with group members in a multi-user, process-design-kit-managed, version-controlled design environment and to step up to technical and schedule challenges
 * Excellent written and oral communication skills, including the ability to document designs, participate in reviews, and work with multidisciplinary scientific and engineering teams

Preferred Knowledge, Skills, and Abilities:

 * Master's or Ph.D. in electrical engineering, computer engineering, applied physics, or a closely related field of study
 * Experience with readout integrated circuits for radiation detectors, including detector timing, triggering, sparsified data readout, high-speed data transmission, calibration, and slow-control functions
 * Experience with ASICs for particle physics, nuclear physics, photon sciences, cryogenic instrumentation, space or radiation environments, or other scientific applications
 * Experience with digital implementation tools and flows such as synthesis, static timing analysis, formal equivalence checking, lint, CDC/RDC analysis, power analysis, DFT/scan, and automated place and route
 * Familiarity with common on-chip bus and control interfaces such as AXI, AHB, APB, Wishbone, I2C, SPI, JTAG, and custom detector-readout protocols
 * Experience with scripting and automation using Tcl, Python, Perl, Make, shell scripting, or similar tools in an EDA environment
 * Knowledge of radiation-tolerant design techniques, single-event-effect mitigation, triple modular redundancy, error detection/correction, and design approaches for low-power or cryogenic operation
 * Experience working with firmware, FPGA prototyping, board-level test systems, and laboratory characterization of ASICs

## Description

We seek a motivated Senior Digital ASIC Design Engineer to join our team as a senior digital designer for developing advanced readout ASICs and system-on-chip architectures for scientific instrumentation. The successful candidate will contribute to microelectronics for the Electron-Ion Collider (EIC), including ePIC detector systems, while also supporting ASICs for other programs in high-energy physics, nuclear physics, photon sciences, quantum information science, and related instrumentation efforts at BNL and with external partners.

In this role, you will lead the architecture, RTL design, implementation, and integration of digital blocks and subsystems for mixed-signal ASICs used in detector readout, trigger and timing distribution, data concentration, control, calibration, and high-speed data transmission. You will collaborate closely with analog and mixed-signal designers, verification engineers, physical design engineers, firmware developers, detector scientists, and other technical team members in the ASIC group, the Instrumentation Division, and the broader scientific community. We look for candidates with strong digital ASIC design expertise, particularly in low-power, radiation-aware, timing-critical, and data-intensive systems for scientific applications.

Our science and engineering challenges are complex and unique! We are engaged in the development of ASICs for particle detectors, high-resolution X- and gamma-ray spectrometers, high-rate photon counters and imagers, cryogenic and radiation-tolerant instrumentation, and other specialized systems for high-energy physics, nuclear physics, photon sciences, quantum information science, and related scientific programs. Our ASICs may operate in extreme environments, must meet stringent power, timing, noise, and radiation requirements, and must integrate reliably with sensors, FPGAs, data acquisition systems, and laboratory test infrastructure. The applications of these ASICs extend beyond BNL to national and international user facilities: your work will have the potential to shape the instruments used for scientific discovery and engineering advancements across the globe!, * Take a lead role in the architecture, microarchitecture, RTL design, and integration of digital ASICs and digital subsystems for scientific instruments, including EIC detector readout and related programs

 * Develop design specifications based on detector, data acquisition, timing, power, radiation, and system integration requirements in conjunction with scientists, engineers, and project stakeholders
 * Design and implement synthesizable RTL in SystemVerilog/Verilog for blocks such as data formatting, sparsification, buffering, trigger and timing interfaces, configuration and control, calibration logic, digital signal processing, and high-speed link interfaces
 * Develop and maintain reusable digital IP, register maps, bus interfaces, clock and reset architectures, memory interfaces, finite-state machines, FIFOs, error detection/correction logic, and monitoring features suitable for ASIC integration
 * Carry out or contribute to synthesis, static timing analysis, clock-domain crossing analysis, reset-domain crossing analysis, power estimation, linting, design-for-test insertion, and timing-driven physical implementation in Cadence, Synopsys, Siemens, or similar CAD/EDA environments
 * Work closely with physical design and analog/mixed-signal teams to ensure successful floorplanning, partitioning, timing closure, power integrity, signal integrity, and mixed-signal integration
 * Coordinate with verification engineers to define verification plans, develop self-checking test benches, review functional coverage, debug simulations, and close design issues before tapeout
 * Support FPGA prototyping, laboratory evaluation, test-board development, bring-up, characterization, and integration of ASICs with sensors, firmware, and data acquisition systems
 * Lead technical documentation, design reviews, interface control documents, and contributions to new project initiatives and proposals making use of emerging microelectronics technologies


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