> Markdown version of [/jobs/ext/1427587-senior-staff-digital-design-engineer](https://www.wearedevelopers.com/jobs/ext/1427587-senior-staff-digital-design-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior Staff Digital Design Engineer - **Company:** Inc. (osi) - **Location:** Plano, TX, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Adobe InDesign, Agile Methodology, Very-Large-Scale Integration, Software Debugging, Logic Synthesis of Circuits, Perl (Programming Language), Formal Verification, Python (Programming Language), Cadence Virtuoso, Shell Script, Software Requirements Analysis, SystemVerilog, Tcl (Programming Language), Universal Asynchronous Receiver/Transmitter, Verilog, Data Processing, State Machines, Front End Software Development, Physical Design - **Published:** July 24, 2026 - **Apply:** https://diversityjobs.com/main/sendform/8/8/28176/1/17687307?backUrl=%2Fcareer%2F17687307%2FSenior-Staff-Digital-Design-Engineer-Texas-Plano ## About the Role * B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline * 5+ years of experience in Digital IC Design with strong expertise in RTL design, verification, synthesis, and silicon debug * Strong proficiency in Verilog/SystemVerilog and digital design methodologies * Proven experience in designing complex state machines, control logic, data-processing modules, and mixed-signal interfaces * Hands-on experience with UVM-based verification and industry-standard serial interfaces such as IC, I3C, SPI, and UART * Expertise in low-power design techniques, PPA optimization, CDC/RDC analysis, Lint, Formal Verification, and LEC flows * Strong understanding of STA, synthesis, and implementation-aware design methodologies * Proficiency in Python, Tcl, Perl, or Shell scripting * Experience with Xcelium, Genus, SpyGlass, OneSpin/JasperGold, and familiarity with Innovus, PrimeTime/Tempus, and DFT flows * Experience with ARM-based SoCs and AMBA protocols (AXI/AHB/APB) is a strong advantage * Familiarity with Cadence Virtuoso and mixed-signal design environments is a plus Required Personal Skills * Strong technical leadership, analytical, and problem-solving abilities * Excellent communication, presentation, and customer engagement skills * Self-motivated, agile, results-oriented, and capable of driving projects independently * Effective mentor and collaborative team player * Ability to influence cross-functional teams and deliver in fast-paced environments * Passion for sensor, imaging, and mixed-signal semiconductor technologies * Fluent in written and spoken English ## Description * Lead the architecture, design, integration, and silicon realization of complex digital and mixed-signal subsystems from specification through production * Translate customer and system requirements into optimized RTL architectures and high-quality Verilog/SystemVerilog implementations meeting PPA targets * Drive design quality and signoff through Lint, CDC/RDC, Formal Verification, LEC, synthesis, and timing validation * Collaborate with system, analog, verification, and physical design teams to define specifications and ensure successful product execution * Develop digital control and interface logic for ADCs, analog front-end, power management, sensors, and other mixed-signal IPs * Lead silicon bring-up, debug, root-cause analysis, and design-to-silicon correlation to achieve first-pass silicon success * Serve as a key customer-facing technical lead, presenting architecture, design reviews, and quality metrics, while driving resolution of technical issues * Prepare technical proposals, effort estimates, PPA projections, specifications, and design documentation * Provide technical leadership and drive continuous improvement in design methodologies and best practices ## Related Videos - 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