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# Co-Design Engineer, Google Cloud TPU

- **Company:** Google LLC
- **Location:** Sunnyvale, CA, United States
- **Experience:** Expert
- **Salary:** $192,000.0 - $279,000.0
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Hardware Design, Systems Analysis, Machine Learning, Performance Tuning, Tensorflow, Google Cloud, Pytorch, Deep Learning, Information Technology, Machine Learning Operations
- **Published:** July 25, 2026
- **Apply:** https://dejobs.org/x/x/9C5273F229694E1E834EA12B82B71228/job/

## About the Role

Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain., * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

 * 10 years of experience in computer architecture, chip architecture, or hardware-software co-design.
 * Experience developing systems for performance modeling, simulation, or system analysis., * Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
 * Experience architecting hardware solutions or performance optimizations for large-scale ML training and inference.
 * Experience with deep learning frameworks such as TensorFlow or PyTorch.
 * Deep understanding of ML trends, business drivers, and the software ecosystem.
 * Ability to engage and collaborate with hardware designers, software architects, and ML researchers.

## Description

* Drive the definition and optimization of the hardware/software stack to enable performant training and serving of large ML models.
 * Collaborate with research and modeling teams to innovate on model architectures, focusing on scaling, quality, and their direct impact on hardware performance.
 * Lead the development of configurable architectural simulators and cycle-accurate performance models to quantify microarchitectural optimizations and evaluate architectural decisions.
 * Conduct system-level performance analysis across highly distributed ML systems, innovating new methodologies to balance compute, memory bandwidth, and inter-chip network requirements.
 * Engage with partners across hardware design, compiler development, and ML research to transition architectural innovations from concept to production.


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