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# ASIC Architect

- **Company:** Arasan Chip Systems, Inc.
- **Location:** United States (Remote available)
- **Experience:** Expert
- **Salary:** $200,000.0 - $300,000.0
- **Contract:** Permanent contract
- **Skills:** Communications Protocols, Software Debugging, Perl (Programming Language), Emulators, Field-Programmable Gate Array (FPGA), Python (Programming Language), PCI Express, Static Timing Analysis, Subsystems, SystemVerilog, Tcl (Programming Language), USB, Verilog, Network Switches, Scripting, Application Specific Integrated Circuits, Physical Design, Software Coding
- **Published:** July 27, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=decd0fd8a1ab8a12

## About the Role

IC Design Division * BE /BTech * 10+ Years Experience, * Bachelor of Engineering in Electrical Engineering or Electronics

 * Minimum 10+ years of ASIC/SoC RTL design experience
 * Strong Verilog/SystemVerilog RTL coding skills
 * Hands-on experience with MIPI, DDR, JEDEC and USB protocols
 * Experience with synthesis and static timing concepts
 * Understanding of CDC, RDC, lint, and low-power methodologies

Preferred Qualifications

 * Experience in advanced technology nodes (28nm, 16nm, 7nm and below)
 * Knowledge of ARM-based SoC architectures
 * Experience with low-power design methodologies (UPF/CPF)
 * Familiarity with scripting languages such as Python, Perl, or TCL

 * Experience with emulation or FPGA prototyping platforms
 * Prior silicon bring-up and post-silicon debugging experience

## Description

We are seeking a highly skilled ASIC Design Lead with proven experience in RTL design and development of complex digital and SoC subsystems. The successful candidate will be responsible for architecture implementation, RTL coding, integration, and design closure of high-performance ASIC products. The ideal candidate should possess strong expertise in MIPI, JEDEC, DDR, and USB protocols and be capable of working across all phases of the ASIC development lifecycle.

Protocol Design Scope

 * MIPI CSI-2, DSI2, I3C, UniPro, D-PHY, C-PHY, M-PHY
 * DDR3, DDR4, DDR5, LPDDR4, LPDDR5
 * USB 2.0, USB 3.x, USB Type-C
 * JEDEC UFS, eMMC

 * High-Speed Digital Interfaces
 * SoC Interconnect and Subsystems

Key Responsibilities

RTL Design & Development

 * Develop synthesizable RTL using Verilog/System Verilog
 * * Design and implement digital IPs, controllers, and interface modules for industry standard protocols such as MIPI, DDR, USB, PCIe, AXI and APB/AHB.
 * Participate in microarchitecture definition and RTL design reviews
 * Perform block-level integration and SoC-level design activities
 * Optimize RTL designs to meet area, power, performance and timing targets.

*Support synthesis, timing closure, and design-for-test (DFT) activities as required.

Design Verification Support

 * Collaborate with verification teams to define verification strategies and test plans
 * Support debug and resolution of functional issues during simulation and silicon bring-up
 * Review coverage metrics and verification results

Implementation & Sign-Off Support

 * Support synthesis, lint, CDC, RDC, and timing closure activities
 * Work closely with Physical Design and DFT teams for successful tape-out


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