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# System IP/RTL Design Engineer

- **Company:** Xoriant Corporation
- **Location:** Austin, TX, United States
- **Salary:** $187,200.0
- **Contract:** Permanent contract
- **Skills:** JIRA, C++ (Programming Language), Software Debugging, Perl (Programming Language), Python (Programming Language), Unix Shell, SystemVerilog, Tcl (Programming Language), Verilog, Caching, Git, Power Analysis (Cryptography), Front End Software Development, Physical Design, Jenkins, Programming Languages
- **Published:** July 28, 2026
- **Apply:** https://www.dice.com/job-detail/2a7bc2af-f743-45c8-9328-4c3492c5c031

## About the Role

* Proficient in RTL design using Verilog and System Verilog
 * Experienced in setting up and maintaining front-end tools for Synthesis, LEC, Lint and Low Power Analysis
 * Excellent debug and problem-solving skills. Experienced in Silicon bring-up activities
 * Experienced in timing and coverage closure
 * Proficient with UNIX/Linux and programming languages such as PERL, Python, TCL, and Unix Shell Scripting
 * Prior experience of having worked with interconnects, caches and/or cache coherency would be an added advantage

Preferred candidate will possess the following:

 * Verilog/System Verilog
 * GIT
 * Perl
 * Python
 * Tcl/Tk
 * C/C++
 * Jenkins, Jira

## Description

* Work on RTL design of System IP blocks
 * Work independently while closely collaborating with other designers as well as members of verification, physical design, performance and power teams
 * Work on developing and maintaining Front-End Tools, Flows and Methodologies
 * Work on creating scripts that automate repetitive daily tasks of team members Support Silicon bring-up activities


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