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# HBM Logic Architect

- **Company:** SK hynix
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $150,000.0 - $320,000.0
- **Contract:** Permanent contract
- **Skills:** Dynamic Random-Access Memory, Application Specific Integrated Circuits, Physical Design
- **Published:** July 30, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=7c4ad534a842235f

## About the Role

* Bachelor's degree or higher in Electrical Engineering or a related discipline(Master's preferred).
 * 5+ years of relevant experience in semiconductor, ASIC/SoC, digital IP, memory, or PHY design.
 * High-speed digital PHY or high-speed IP design and analysis
 * DRAM memory controller design and analysis
 * DRAM DFT/DFD architecture, design, or analysis
 * PHY/TSV bit macro design, TSV PHY hard macro design, or 3D PHY design
 * Experience in PPA (Power, Performance, Area) optimization, preferred.

## Description

This role involves establishing close technical engagement with key US-based customers to address immediate base-die architectural challenges in HBM and 3D-stacked DRAM. You will be responsible for building a compact and focused HBM Architect Design team in the US to directly support these critical customer interactions. The position also requires developing advanced and customized HBM architectures for future products while strengthening competitiveness through sustained collaboration and technical leadership., * Define, design, and validate digital IP for ASIC/SoC products.

 * Perform RTL design and implementation based on approved specifications.
 * Collaborate with cross-functional teams to define IP functionality, behavior, and architecture.
 * Review digital IP requirements and evaluate architecture options based on PPA targets.
 * Determine or contribute to architecture decisions for digital IP implementation.
 * Develop and verify RTL designs using industry-standard design methodologies.
 * Provide design guidance and support for physical design implementation.
 * Strengthen digital IP design capabilities for HBM and next-generation DRAM development by securing personnel for real-time support near customer sites.
 * Drive system-level co-optimization beyond standalone DRAM design.
 * Build deep technical partnerships with U.S.-based customers.
 * Improve competitiveness through close engagement with customers in the U.S.


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