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# Senior Digital Design Engineer, IP and Methodology

- **Company:** Astera Labs
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $135,000.0 - $195,000.0
- **Contract:** Permanent contract
- **Skills:** Microarchitecture, Logic Synthesis of Circuits, Ethernet, Firmware, Formal Verification, Python (Programming Language), Key Management, PCI Express, Reduced Instruction Set Computing, SystemVerilog, Systems Integration, Application Specific Integrated Circuits, U-Boot, Physical Design
- **Published:** May 15, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=1b8a95315c56f9e1

## About the Role

Do you have experience in SystemVerilog?, * Bachelor's degree in Electrical Engineering or equivalent

 * 3+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets
 * Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence
 * Experience with CPU subsystem design or embedded processor integration (RISC-V, ARM, or similar architectures)
 * Understanding of security fundamentals in silicon design (secure boot, root of trust, cryptographic implementations)
 * Experience with clocking, CDC, and RDC methodologies
 * Proficiency in SystemVerilog and Python in a production environment, * Experience designing or integrating security IP (cryptographic accelerators, secure enclaves, key management)
 * Familiarity with high-speed protocols-PCIe Gen 6/7, Ethernet, UALink, or UCI
 * Experience with CMOS nodes (7nm)
 * Exposure to embedded firmware development or secure firmware boot flows
 * Experience with functional and formal verification at block and chip level
 * Familiarity with UVM-based verification methodologies

Base salary range is $135,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

## Description

* RTL Design & Implementation
 + Own the RTL implementation of complex digital designs from micro-architecture through sign-off
 + Design and implement CPU subsystems and embedded processor interfaces
 + Develop security-focused digital blocks including secure boot, cryptographic engines, and trusted execution environments
 * Verification & Quality
 + Collaborate with verification teams to review test plans and debug issues
 + Support efforts to achieve timing closure and implement Design-for-Test (DFT) features
 + Accountable for quality and overall design success with the support of senior engineers
 * Methodology & Automation
 + Scripting and automation for ASIC methodology improvement
 + Contribute to design infrastructure that improves team productivity and design quality


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