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# ASIC II - AMZ10016730

- **Company:** Amazon.com, Inc.
- **Location:** Austin, TX, United States
- **Salary:** $136,000.0 - $184,000.0
- **Contract:** Permanent contract
- **Skills:** Data Analysis, Code Coverage, Software Debugging, System Testing, Application Specific Integrated Circuits
- **Published:** July 10, 2026
- **Apply:** https://www.amazon.jobs/en/jobs/10470000/asic-ii-amz10016730

## About the Role

Bachelors degree or foreign equivalent degree in Engineering, Physical Sciences, or a related field and two years of experience in the job offered or a related occupation. Must have one year of experience in the following skill(s): (1) working with semiconductor manufacturing flows, advanced technology nodes, ATE and SLT testing, and yield analysis; and (2) experience with debug, root cause, and corrective action to resolve manufacturing or quality issues., Bachelors degree or foreign equivalent degree in Engineering, Physical Sciences, or a related field and two years of experience in the job offered or a related occupation. Must have one year of experience in the following skill(s): (1) working with semiconductor manufacturing flows, advanced technology nodes, ATE and SLT testing, and yield analysis; and (2) experience with debug, root cause, and corrective action to resolve manufacturing or quality issues.#0000

## Description

Perform detailed data analysis of semiconductor manufacturing ATE Test and System test data to optimize yield, test time, and implement optimal screening methodologies across platforms. Lead structural (Scan ATPG, MBIST) test coverage improvements with new coverage methods like SDD, Cell Aware, Bridge Aware using various UDFM models at ATE and system levels, by defining and running DOEs to characterize and evaluate these. Lead effort to bring-up and build volume scan diagnosis abilities and guide scan yield debug and failure analysis activities for future ML chips to drive faster yield ramps and entitlement yield achievement. Foster strong stakeholder relationships and drive corrective actions for yield and quality improvements through effective collaboration with test engineering, system validation, and DFT teams. Power and performance characterization to define the mission mode operating V/F model.


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