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# Wireless PHY Design Verification Engineer

- **Company:** Apple Inc.
- **Location:** San Diego, CA, United States
- **Salary:** $120,300.0 - $210,100.0
- **Contract:** Permanent contract
- **Skills:** Bluetooth, Data Transmissions, Software Debugging, Digital Technology, IEEE 802.11, Issue Tracking Systems, Systems Development Life Cycle, SystemVerilog, Wi-Fi Technology, Application Specific Integrated Circuits, Low Latency, Hardware Acceleration
- **Published:** May 29, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=05e15e760df93a12

## About the Role

Do you have experience in Verification (System development task)?, Do you have a Bachelor's degree?, Knowledge of IEEE 802.11 wireless protocols, Bluetooth, Cellular, or similar communication systems.

Experience with applying / integrating System models utilizing DPIs.

Understanding of DSP algorithms verification strategies (Bit / Cycle matching, Assertions).

Experience with transaction-level modeling including packet-based approaches (scoreboarding, protocols).

Minimum Qualifications

Minimum requirement of a bachelor's degree.

Track record of several tapeout cycles of sophisticated designs.

Experience verifying wireless, DSP, or digital communication systems.

Knowledge of ASIC verification flows with SystemVerilog / UVM including testbench architecture, scenario creation, and coverage-driven methodologies.

Experience developing verification environments, bringing up complex designs, and debugging simulations.

Experience with constrained random testing, functional coverage implementation, and assertion-based verification.

## Description

As a Wireless PHY Design Verification Engineer, you'll verify sophisticated WiFi PHY digital systems spanning time/frequency-domain processing, hardware acceleration, calibration engines, and protocol implementation. You'll architect verification strategies for high-rate, low-power, low-latency, and multi-link wireless features enabling advanced applications across Apple's product ecosystem. You'll own subsystem verification from test planning through coverage closure-building environments, constrained random scenarios, and applying analytics methodologies to deliver exceptional wireless silicon.","responsibilities":"Develop sophisticated UVM environments and bus functional models for complex DSP subsystems and IEEE 802.11 protocol.

Own subsystem verification from test planning and environment bring-up through feature closure.

Develop UVM testbench environments, bus functional models (BFMs), assertions, and infrastructure / DPIs to utilizing algorithm models.

Architect and implement constrained random scenarios exercising complex protocol interactions.

Apply data-driven verification closure through coverage tracking, issue tracking, gap identification, and metrics.

Drive verification strategy with cross-functional Systems / Design teams to achieve coverage closure across complex domains.


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