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# RTL Design Engineer

- **Company:** SYNAPSE BUSINESS SYSTEMS INCORPORATED
- **Location:** United States (Remote available)
- **Experience:** Expert
- **Salary:** $135,200.0 - $145,600.0
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Microarchitecture, Software Debugging, Formal Verification, Hardware Design, System on a Chip, SystemVerilog, Verilog, Backend, Code Inspection
- **Published:** May 31, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=6cd67ee4d88983cb

## About the Role

Do you have experience in Verilog?, * 5+ years of hands-on RTL design experience (SystemVerilog / Verilog)

 * Strong understanding of micro-architecture and RTL implementation from specs
 * Experience in DSP hardware implementation (filtering, FFT, etc.)
 * Knowledge of SoC design flows: CDC, power domains, timing constraints, formal verification
 * Experience with synthesis, linting, simulation, and STA tools
 * Understanding of DFT concepts (scan, BIST)
 * Strong debugging and problem-solving skills
 * Good communication and ability to work in cross-functional teams

## Description

We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will design and implement high-performance digital blocks and work closely with architecture, analog/mixed-signal, and verification teams to deliver production-quality silicon., * Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog/Verilog

 * Translate architectural and algorithmic specifications into synthesizable RTL
 * Implement DSP blocks such as filtering, FFT/IFFT, beamforming, etc.
 * Develop RTL for SoC components including interfaces, clock/reset, power management, and debug logic
 * Work with internal and external IP integration into chip-level designs
 * Collaborate with AMS teams on digital-analog interfaces, calibration logic, and control systems
 * Drive PPA (power, performance, area) optimization and support timing closure with backend teams
 * Participate in design reviews, integration, synthesis, and timing closure activities
 * Support silicon bring-up and lab validation of digital sub systems


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