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# Fpga Engineer (Valencia)

- **Company:** Em&e Group
- **Location:** Valencia, Spain
- **Contract:** Permanent contract
- **Skills:** Boolean Algebra, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Field-Programmable Gate Array (FPGA), Hardware Description Language, Joint Test Action (IEEE Standards), Python (Programming Language), Requirements Traceability, Static Timing Analysis, SystemVerilog, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Vivado, ModelSim
- **Published:** July 27, 2026
- **Apply:** https://www.buscojobs.com.es/fpga-engineer-valencia-en-valencia-ID-364657866

## About the Role

Degree or Master's in Telecommunications Engineering, Electronics, Computer Engineering, or related fields.
3-5 years of proven experience in the full FPGA design cycle and lab validation.
Specialization in microelectronic design, digital architectures, and verification flows.
Proficiency in HDL languages (VHDL, Verilog, SystemVerilog) and vendor tools (Vivado, Quartus).
Experience
#J-*****-Ljbffr

## Description

At DAS Photonics, part of EM&E, we are pioneers in the design and development of cutting?edge photonic solutions for the aerospace and defense sectors. Our technologies power next?generation missions, ensuring superior performance, reliability, and innovation in every system we deliver.The RoleIn this role, you will design, implement, and validate digital logic on FPGAs, defining RTL architectures in line with system technical specifications. Your work will be critical to ensuring the functional and timing correctness of the hardware, the reliable integration of high?speed component.Key ResponsibilitiesDesign, implement, and validate digital logic in FPGA (VHDL, Verilog, SystemVerilog), defining RTL architectures to meet technical specifications.Develop and maintain designs in Vivado, Quartus or equivalent tools, covering synthesis, place & route, timing analysis, and timing closure.Create testbenches, run functional and timing simulations (ModelSim/Questa), and perform co simulation.Perform bring?up and debugging using oscilloscopes, logic analyzers, and JTAG, ensuring full requirements traceability.Automate synthesis, simulation, and validation tasks via scripting (TCL, Python) to improve repeatability and efficiency.Apply best practices in digital design (CDC, reset, reliability) and comply with sector standards (ECSS, DO-254 where applicable).Generate full technical documentation and participate in technical reviews (PDR, CDR, QR/AR).Support internal and external audits with complete traceability throughout the FPGA design lifecycle.About youDegree or Master's in Telecommunications Engineering, Electronics, Computer Engineering, or related fields.3-5 years of proven experience in the full FPGA design cycle and lab validation.Specialization in microelectronic design, digital architectures, and verification flows.Proficiency in HDL languages (VHDL, Verilog, SystemVerilog) and vendor tools (Vivado, Quartus).Experience#J-*****-Ljbffr


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