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# Digital Design Engineer

- **Company:** Infineon Technologies AG
- **Location:** Spain
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, ARM Architecture, Code Coverage, Digital Electronics, Logic Synthesis of Circuits, Requirements Management, Static Timing Analysis, SystemVerilog, Verilog, Jama (Software), Front End Software Development, Programming Languages
- **Published:** July 13, 2026
- **Apply:** https://www.jobleads.com/es/job/e3445d1e542eef907d1c36b12d7d69d1d

## About the Role

* Master's degree in Electrical Engineering with a focus on Digital Integrated Circuit Design or equivalent.
 * 3+ years professional experience in digital IC front-end design covering architecture, specification, modeling, timing analysis, design-for-test strategies and verification.
 * Experience with advanced MCU/bus-system based digital architectures (e.g. ARM Cortex-M/AHB/AXI).
 * Proficiency with coding languages and CAD tools for digital IC design and verification (Verilog, System-Verilog, synthesis, lint, CDC, STA, IR-Drop, ATPG).
 * Experience with formal requirements management tools (e.g. Jama, Doors).
 * Exceptional teamwork, collaborative and respectful attitude; dedicated to team success.
 * Fluency in English and excellent communication/ listening skills.

## Description

As a Staff Digital Design Engineer in the Research & Development team, you will merge creativity with technical expertise to shape future technology, drive groundbreaking projects, and bring new ideas to life., * Elaborate and capture digital module requirements in collaboration with System/Digital Architects and the Analog Design team, focusing on Analog-Digital interfacing.

 * Develop digital block architecture with Automotive quality, testability and safety requirements (ISO26262), including RTL design, state-machine design, synchronization, clock gating, low-power strategies, mixed-signal interfacing, static timing analysis, design-for-test, clock-domain-crossing, etc.
 * Verify digital design at block and top-level with UVM environment; perform fault injection simulations per ISO26262.
 * Synthesize digital RTL using state-of-the-art tools, ensuring DFT, low-power and safety compliance.
 * Collaborate with Digital Place & Route team, execute gate-level simulation, and contribute to continuous improvement of digital design methodology, best practices, guidelines.
 * Conduct requirements/architecture/design reviews and produce relevant block design and sign-off documentation.
 * Work closely with Test Development Engineers on Design-for-Test strategy to meet Automotive test coverage; support ATPG pattern generation and simulation.


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