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# ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration

- **Company:** Annapurna Labs
- **Location:** Austin, TX, United States
- **Experience:** Experienced
- **Salary:** $136,000.0 - $212,800.0
- **Contract:** Internship / Graduate position
- **Skills:** Amazon Web Services, Code Review, Data Centers, Software Debugging, Software Design Patterns, Machine Learning, Azure Machine Learning, Software Engineering, System on a Chip, SystemVerilog, Application Specific Integrated Circuits, Information Technology, Build Process, Software Coding, Software Version Control
- **Published:** July 4, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=9d447d6c2527a0e0

## About the Role

The ideal candidate will have a strong background in ASIC design, proficiency in SystemVerilog, and excellent analytical and problem-solving skills. Experience with high-performance and power-efficient designs is highly desirable.

You will thrive in this role if you:

 * Have a "Learn and Be Curious" mindset
 * Have familiarity with key components such as interconnects, DMAs, Memory sub-systems, accelerator engines, debug and system level architectures
 * Have a strong drive to innovate, explore new solutions, and contribute to the company's intellectual property through patents, * Bachelor's degree or equivalent
 * 3+ years of non-internship design or architecture (design patterns, reliability and scaling) of new and existing systems experience, * Master's degree in computer science or equivalent
 * 3+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience

## Description

Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs., As an ASIC Design Engineer, you will:

 * Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets

 * Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements

 * Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints

 * Execute lint and clock domain crossing quality checks to ensure design integrity

 * Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts


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