> Markdown version of [/jobs/ext/1696114-principal-fpga-asic-verification-engineer-onsite](https://www.wearedevelopers.com/jobs/ext/1696114-principal-fpga-asic-verification-engineer-onsite). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Principal FPGA/ASIC Verification Engineer (Onsite) - **Company:** RTX - **Location:** Fort Wayne, IN, United States - **Experience:** Experienced - **Salary:** $107,500.0 - $204,500.0 - **Contract:** Permanent contract - **Skills:** C (Programming Language), C++ (Programming Language), Code Coverage, Software Debugging, Perl (Programming Language), Formal Verification, Field-Programmable Gate Array (FPGA), Revision Control Systems, Integrated Development Environments, Python (Programming Language), Oracle Virtual Machine, Signal Processing, Software Engineering, Subversion, SystemVerilog, Test Case, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Scripting, Application Specific Integrated Circuits, Git - **Published:** July 3, 2026 - **Apply:** https://globalhr.wd5.myworkdayjobs.com/REC_RTX_Ext_Gateway/job/US-IN-FT-WAYNE-150A--1010-Production-Rd--BLDG-150A/Principal-FPGA-ASIC-Verification-Engineer--Onsite-_01857075-1 ## About the Role Active and transferable U.S. government issued security clearance is required prior to start date. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance, * Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 8 years prior relevant experience or an Advanced Degree in a related field and minimum 5 years of experience * Active and transferable U.S. government issued security clearance is required prior to start date * U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance * Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment. * At least 4+ years experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment. * Demonstrated ability to work independently and lead and/or mentor junior engineers within a team environment * Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog. * 4+ years of experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog) * Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity., * Experience with ASIC/FPGA lab validation and debug using standard lab equipment, along with familiarity with DFT, manufacturability, and production test concepts. * Proficiency with Unix/Linux environments, scripting or software development (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado. * Strong written and verbal communication skills, with the ability to work independently and collaboratively in fast-paced, multidisciplinary engineering environments. ## Description We are seeking an experienced and highly motivated Principal Electrical or Computer Engineer to lead the design, implementation, and verification of advanced testbenches for a portfolio of high-performance digital ASICs and FPGAs. In this role, you will drive the development of cutting-edge signal processing and information assurance technologies supporting critical Mission Systems programs as part of the Microelectronics Technology team. This candidate will be onsite based out of Fort Wayne, IN. What You Will Do * Verification environment architecture and design using SystemVerilog with OVM/UVM * Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking * Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow * Contribute to engineering estimates for new program pursuits. * Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status ## Related Videos - [How a Small Team Shrank a Microsoft Monorepo by 94%](https://www.wearedevelopers.com/videos/1236-how-a-small-team-shrank-a-microsoft-monorepo-by-94) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Git for Code Reviews](https://www.wearedevelopers.com/videos/429-git-for-code-reviews) - [You don't need to write the code. You need to become a verification architect and prove it's correct](https://www.wearedevelopers.com/videos/100023-you-don-t-need-to-write-the-code-you-need-to-become-a-verification-architect-and-prove-it-s-correct) - [When testing just doesn’t cut it](https://www.wearedevelopers.com/videos/720-when-testing-just-doesn-t-cut-it) - [Stop Committing Your Secrets - GIt Hooks To The Rescue!](https://www.wearedevelopers.com/videos/573-stop-committing-your-secrets-git-hooks-to-the-rescue) ## Related Articles - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Fully Remote Software Engineer Jobs](https://www.wearedevelopers.com/magazine/447-fully-remote-software-engineer-jobs) - [Should senior developers refuse interview coding challenges?](https://www.wearedevelopers.com/magazine/29-should-senior-developers-refuse-interview-coding-challenges) - [Where to Find Entry-Level Software Engineering Jobs](https://www.wearedevelopers.com/magazine/397-where-to-find-entry-level-software-engineering-jobs) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers)