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# FPGA Engineer - P3

- **Company:** Butler America, LLC
- **Location:** Tucson, AZ, United States
- **Experience:** Expert
- **Salary:** $145,600.0 - $170,560.0
- **Contract:** Permanent contract
- **Skills:** Systems Engineering, Configuration Management, Code Coverage, Computer Engineering, Software Debugging, Linux, Digital Electronics, Logic Synthesis of Circuits, Field-Programmable Gate Array (FPGA), SAP (Applications), Software Requirements Analysis, SystemVerilog, VHSIC Hardware Description Language (VHDL), Vivado, Software Verification, Fpga Hardware, Physical Design, Software Coding
- **Published:** July 21, 2026
- **Apply:** https://public-rest34.bullhornstaffing.com/rest-services/31DK90/query/JobBoardPost?where=id=72743&fields=id,title,publishedCategory(id,name),address(city,state),employmentType,dateLastPublished,publicDescription,isOpen,isPublic,isDeleted

## About the Role

Work independently with minimal oversight. Follow standard department development processes. Required and Desired Qualifications Core Technical Skills (Non negotiables)
Bachelor's degree in electrical engineering (will consider degrees in Computer Engineering and Electrical Engineering Technology.
Minimum of 5 years of experience to include at least 1 of the following: Digital design and VHDL coding Xilinx or Microsemi devices and flow tools Delivering FPGA solutions to system level applications Hands on experience with integration and debug.
A US Security clearance prior to the start date. (US citizenship is required as only US citizens are eligible for a security clearance.
Ability to attain Special Program Access (SAP).Desired Skills (Nice to Have) FPGA design experience in one or more of the following areas: Radar processing techniques Image processing techniques for visual and infrared sensors Embedded systems design using ARM, Microblaze, or Nios processors Gigabit serial interfaces and multi gigabit transceivers (MGTs) Constrained random verification in UVM using System Verilog Verification utilizing emulation platforms, such as Veloce
Day to Day Responsibilities (3Â?5 bullets max) Design and deliver production quality FPGA releases from initial proof of concept up to production Architect FPGA based systems to determine parts, interfaces, and Concept of Operations (CONOPS) Translate system level requirements into FPGA requirements Design and code in VHDL for reliability and maintainability Verify designs utilizing self checking techniques with directed and constrained random tests, while tracking functional and code coverage Help drive projects and execute to program schedules on time and budget Create complete documentation including requirements, verification plan, and users guides May support internal and external technical reviews

Tools / Technologies Required
Linux
FPGA Design and Verification tools (i.e. Xilinx Vivado, Siemens Questasim)
Minimum 5 years of experience required.

Education Required:
Bachelor's degree in electrical engineering (will consider degrees in Computer Engineering and Electrical Engineering

## Description

Project Overview The Effector Digital Products department is seeking an Electrical Engineer with FPGA development or verification experience to join our team. We are looking for candidates willing to collaborate, innovate, and team with our engineers to generate and utilize today's cutting edge technology to design and verify FPGAs that implement missile guidance, video and digital signal processing. Our technology base includes high speed digital electronics, configurable logic, and homogeneous / heterogeneous multiprocessor designs. Position Overview In this role you will develop FPGA designs for all major vendors and device families including: Xilinx, Altera, and Microsemi. Designs are implemented using VHDL for the following applications: gigabit serial interfaces, Radio Frequency (RF) and Electro Optical (EO) DSP, controls, data links, embedded processing and processor interfaces. Designers work with circuit card designers and systems engineers to develop requirements, architect new
parts, collaborative modeling of algorithms, partition and perform code development, simulation, and place and route.
Designs are verified against requirements using both directed test and constrained random methodologies. Design support is expected from requirements definition through integration and test. Design documentation and configuration management are required.


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