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# System and Scheduling Architect - GPU

- **Company:** NVIDIA Ltd.
- **Location:** Santa Clara, CA, United States
- **Experience:** Experienced
- **Salary:** $124,000.0 - $195,500.0
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Nvidia CUDA, Perl (Programming Language), Firmware, Python (Programming Language), Machine Learning, OpenGL, PCI Express, Subsystems, Systems Architecture, Graphics Processing Unit (GPU), Information Technology
- **Published:** July 12, 2026
- **Apply:** https://www.juju.com/job/00000000gfrx7q

## About the Role

+ BS or MS in Compute Architecture, Computer Science, or Electrical Engineering (or related degree) or equivalent experience

 + 2+ years of meaningful work experience

 + Work experience coding in C or C++

 + Course work or industry experience in Computer Architecture, Operation systems, and/or system architecture

Ways to stand out from the crowd:

 + Knowledge of memory isolation and security, firmware, process scheduling, OpenGL, DX, CUDA, DL/ML, PCIe, AXI, NVLink, and/or CXL

 + Knowledge of Perl or Python

## Description

We are now looking for a GPU system and process scheduling architect! NVIDIA is seeking outstanding system architects to design the next generation GPU system interface. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting the field of artificial intelligence and product lines ranging from consumer graphics to self-driving cars. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform of tomorrow.

What you'll be doing:

 + As a member of the architecture team, you will be responsible for understanding how the GPU sub-system modules interoperate and interact with overall system

 + You will architect and plan features in concert with software, hardware, and verification teams across the globe to implement the next iteration of GPUs

 + Create functional and performance models, often in C++, along with test plans to validate the features you design

 + Actively support post-silicon validation activities


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