> Markdown version of [/jobs/ext/1722345-senior-asic-fpga-verification-engineer-onsite](https://www.wearedevelopers.com/jobs/ext/1722345-senior-asic-fpga-verification-engineer-onsite). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior ASIC/FPGA Verification Engineer (Onsite) - **Company:** RTX - **Location:** Fort Wayne, IN, United States - **Experience:** Expert - **Salary:** $86,800.0 - $165,200.0 - **Contract:** Permanent contract - **Skills:** Code Coverage, Software Debugging, Ethernet, Formal Verification, Field-Programmable Gate Array (FPGA), Integrated Development Environments, Oracle Virtual Machine, PCI Express, Software Engineering, Subversion, SystemVerilog, Test Case, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Scripting, Application Specific Integrated Circuits, Git, Software Version Control - **Published:** July 3, 2026 - **Apply:** https://globalhr.wd5.myworkdayjobs.com/REC_RTX_Ext_Gateway/job/US-IN-FT-WAYNE-150A--1010-Production-Rd--BLDG-150A/Senior-ASIC-FPGA-Verification-Engineer--Onsite-_01857070 ## About the Role Active and transferable U.S. government issued security clearance is required prior to start date. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance, * Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field and minimum 3 years of experience * Active and transferable U.S. government issued security clearance is required prior to start date * U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment. * Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog. * Working knowledge of chip-level verification methodologies, including constrained-random testing, functional coverage, and assertion-based verification using SystemVerilog. * Proficiency with revision control concepts and tools (e.g., Git, Subversion), * Excellent communication and teamwork skills with the ability to work in a collaborative environment. * Experience with high-speed digital interfaces and protocols (e.g., DDR, PCIe, Ethernet) * Experience with ASIC/FPGA lab validation and debug using standard lab equipment * Proficiency with industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado * Background in aerospace, defense, or mission-critical systems * Proficiency with Unix/Linux environments, scripting or software development ## Description Collins Aerospace is seeking a highly skilled and innovative Senior ASIC/FPGA Verification Engineer to join our Applied Research and Technology (ART) Microelectronics Technology team. Your work will contribute to the development of cutting-edge defense solutions across Mission Systems, leveraging your expertise in chip-level verification methodologies of a wide variety of high-performance digital FPGAs & ASICs. This candidate will be onsite based out of Fort Wayne, IN. What You Will Do * Verification environment architecture and design using SystemVerilog with OVM/UVM * Creation of written test plans, testcases, code coverage tracking, and functional coverage tracking * Testbench development for the verification of RTL blocks using VHDL or SystemVerilog * Collaborate with design engineers in the integration and validation of ASIC/FPGA solutions * Provide technical guidance and mentorship to junior engineers * May provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status * Contribute to engineering estimates for new program pursuits. ## Related Videos - [How a Small Team Shrank a Microsoft Monorepo by 94%](https://www.wearedevelopers.com/videos/1236-how-a-small-team-shrank-a-microsoft-monorepo-by-94) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Git for Code Reviews](https://www.wearedevelopers.com/videos/429-git-for-code-reviews) - [You don't need to write the code. You need to become a verification architect and prove it's correct](https://www.wearedevelopers.com/videos/100023-you-don-t-need-to-write-the-code-you-need-to-become-a-verification-architect-and-prove-it-s-correct) - [When testing just doesn’t cut it](https://www.wearedevelopers.com/videos/720-when-testing-just-doesn-t-cut-it) - [Stop Committing Your Secrets - GIt Hooks To The Rescue!](https://www.wearedevelopers.com/videos/573-stop-committing-your-secrets-git-hooks-to-the-rescue) ## Related Articles - [Fully Remote Software Engineer Jobs](https://www.wearedevelopers.com/magazine/447-fully-remote-software-engineer-jobs) - [Where To Find Software Engineering Jobs](https://www.wearedevelopers.com/magazine/396-where-to-find-software-engineering-jobs) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Find a Developer Job: 12 Best Job Sites For Developers](https://www.wearedevelopers.com/magazine/165-find-a-developer-job-12-best-job-sites-for-developers) - [How Much FAANG Companies Actually Pay Software Engineers in 2025](https://www.wearedevelopers.com/magazine/230-how-much-faang-companies-actually-pay-software-engineers-in-2025)