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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Sr. DFT Design Engineer, AWS Machine Learning Acceleration - **Company:** Amazon.com, Inc. - **Location:** Austin, TX, United States - **Experience:** Expert - **Salary:** $159,200.0 - $215,300.0 - **Contract:** Permanent contract - **Skills:** Amazon Web Services, Code Review, Microarchitecture, Data Centers, Software Debugging, Perl (Programming Language), Field-Programmable Gate Array (FPGA), Joint Test Action (IEEE Standards), Python (Programming Language), Machine Learning, Azure Machine Learning, System on a Chip, Tcl (Programming Language), Application Specific Integrated Circuits, Software Verification, Information Technology, Physical Design - **Published:** July 2, 2026 - **Apply:** https://www.jobmonkeyjobs.com/career/27815457/Sr-Dft-Design-Engineer-Aws-Machine-Learning-Acceleration-Texas-Austin-7375 ## About the Role Bachelor's degree in computer science, electrical engineering, or related field - 5+ years of practical semiconductor ASIC design work including owning end to end design of major SOC blocks experience - Knowledge about industry standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time - Experience with automation script development Preferred Qualifications - Master's degree or Ph.D. degree in Electrical Engineering or related field - Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs - Experience with modern ASIC/FPGA design and verification tools - Experience with SOC bring-up and post-silicon validation - MS degree in computer science, electrical engineering, or related field - Experience with gate-level testing and multi-clock design practices (CDC) - Good breadth of knowledge in chip design from micro-architecture through physical design - Good knowledge of design verification (DV) simulation methodologies - Strong programming and scripting skills in Perl, Python or Tcl - Experience with industry standard DFT/SCAN/ATPG tools - Experience with STA constraints development and analysis for DFT modes - Practical experience with silicon debug ## Description Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team, you'll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems-our custom-designed machine learning inference and training servers. Our success depends on world-class server infrastructure as we handle massive scale and rapidly integrate emerging technologies. We're looking for a Sr. DFT Design Engineer to help us trailblaze new technologies and architectures while ensuring high design quality and making the right trade-offs., * Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes * Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions * Act as the primary point of contact for cross-functional stakeholders (PD, Architecture, and Product Engineering) to align schedules and goals * Mentor and develop junior engineers through code reviews, methodology training, and technical guidance * Manage project timelines and deliverables, ensuring high-quality DFT implementation from RTL through Silicon bring-up ## Related Videos - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Are Code Reviews Worth It? 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