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# Senior Electrical Engineer - ASIC/FPGA (Onsite)

- **Company:** RTX
- **Location:** Fort Wayne, IN, United States
- **Experience:** Expert
- **Salary:** $86,800.0 - $165,200.0
- **Contract:** Permanent contract
- **Skills:** Agile Methodology, Unix, C++ (Programming Language), Computer Graphics, Digital Architecture, Digital Electronics, Perl (Programming Language), Field-Programmable Gate Array (FPGA), Signal Processing, Static Timing Analysis, Subversion, SystemVerilog, Systems Integration, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Scripting, Application Specific Integrated Circuits, ModelSim, Git, Software Version Control
- **Published:** July 1, 2026
- **Apply:** https://globalhr.wd5.myworkdayjobs.com/REC_RTX_Ext_Gateway/job/US-IN-FT-WAYNE-150A--1010-Production-Rd--BLDG-150A/Senior-Electrical-Engineer---ASIC-FPGA--Onsite-_01856011

## About the Role

The ability to obtain and maintain a U.S. government issued security clearance is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance, * Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field and minimum 3 years of experience.

 * The ability to obtain and maintain a U.S. government issued security clearance is required
 * U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance
 * At least 3+ years e experience in RTL coding and simulation in Verilog or VHDL.
 * Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
 * Experience in Testbench development for the verification of RTL blocks using System Verilog.
 * Proficient using ASIC and/or FPGA simulation and synthesis tools (e.g., ModelSim, Synplify, Quartus, Vivado, or other FPGA-specific tools).
 * Familiarity with revision control concepts and tools (e.g., Git, Subversion)., * Familiarity with best-practice chip-level verification techniques and languages (e.g., constrained random, functional coverage, System Verilog).
 * Experience in ASIC / FPGA lab validation using advanced laboratory equipment.
 * Experience in Design for Test (DFT) and manufacturability experience.
 * Experience with Unix, scripting, C/C++, and/or Perl.

## Description

We are looking for a Senior FPGA Engineer to be involved in the design, implementation, verification, and integration of a wide variety of high-performance digital ASICs, FPGAs, and circuit boards applied to computer graphics and supporting communication signal processing and information assurance products.

What Will You Do:

 * Identify requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration.
 * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow.
 * Contribute to engineering estimates for new program pursuits.
 * Provide technical leadership for project design teams by breaking down work, planning activities, and reporting status.
 * Participate in Agile team meetings and planning activities


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